MH1M365CNXJ-5 View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
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MH1M365CNXJ-5 Datasheet PDF : 15 Pages
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MITSUBISHI LSIs
MH1M365CXJ/CNXJ-5,-6,-7
HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
CAPACITANCE (Ta=0 ~ 70 °C, Vcc=5.0V ± 10%, Vss=0V, unless otherwise noted)
Symbol
Parameter
Test conditions
CI (A)
CI (W)
CI (RAS)
CI (CAS)
CI / O
Input capacitance,address inputs
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
VI=Vss
f=1MHZ
Vi=25mVrms
Limits
Unit
Min Typ Max
30
pF
36
pF
36
pF
29
pF
22
pF
SWITCHING CHARACTERISTICS (Ta=0 ~ 70 °C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted , see notes 6,14,15)
Symbol
Parameter
tCAC
tRAC
tAA
tCPA
tOHC
tOHR
tCLZ
tWEZ
tOFF
tREZ
Access time from CAS
(Note 7,8)
Access time from RAS
(Note 7,9)
Column address access time
(Note 7,10)
Access time from CAS precharge
(Note 7,11)
Output hold time from CAS
Output hold time from RAS
(Note 13)
Output low impedance time from CAS low (Note 7)
Output disable time after WE high
(Note 12)
Output disable time after CAS high
(Note 12,13)
Output disable time after RAS high
(Note 12,13)
MH1M365C -5
Min
Max
13
50
25
30
5
5
5
13
13
13
Limits
MH1M365C -6
Min
Max
15
60
30
35
5
5
5
15
15
15
MH1M365C -7 Unit
Min
Max
20
ns
70
ns
35
ns
40
ns
5
ns
5
ns
5
ns
20
ns
20
ns
20
ns
Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 16.4 ms) of RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-5mA) / VOL=0.4V(IOL=-4.2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
8: Assumes that tRCD ≥ tRCD(max) and tASC ≥ tASC(max) and tCP ≥t CP(max).
9: Assumes that tRCD ≤ tRCD(max) and tRAD ≤ tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,
tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD ≥ tRAD(max) and tASC ≤ tASC(max).
11: Assumes that tCP ≤ tCP(max) and tASC ≥ tASC(max).
12: tWEZ(max) ,tOFF(max) and tREZ(max)defines the time at which the output achieves the high impedance state ( IOUT ≤ I ± 10 µA I)
and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both RAS and CAS go to high.
MIT-DS-0084-1.0
MITSUBISHI
ELECTRIC
( 4 / 15 )
Oct.15.96
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