DS1089LU-21G View Datasheet(PDF) - Maxim Integrated

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DS1089LU-21G

3.3V Center Spread-Spectrum EconOscillator™

Maxim Integrated 

DS1089L

3.3V Center Spread-Spectrum EconOscillator™

When dither is enabled (by selecting a dither frequency

setting greater than 0 with SPRD high), the master oscil-

lator frequency is dithered around the center frequency

by the selected percentage from the programmed fMOSC

(see Figure 2). For example, if fMOSC is programmed

to 40MHz (factory setting) and the dither amount is

programmed to ±1%, the frequency of fMOSC will dither

between 39.6MHz and 40.4MHz at a modulation fre-

quency determined by the selected dither frequency.

Continuing with the same example, if J1 = 0 and J0 = 1,

selecting fMOSC/2048, then the dither frequency would

be 19.531kHz.

Register Summary

The DS1089L registers are used to change the dith-

er amount, output frequency, and slave address. A bit

summary of the registers is shown in Table 4. Once

programmed into EEPROM, the settings only need to be

reprogrammed if it is desired to reconfigure the device.

PRESCALER Register

Bits 7 to 6:

Dither Frequency. The J1 and J0 bits

control the dither frequency applied to the

output. See Table 2 for divider settings. If

either of bits J1 or J0 is high and SPRD is

high, dither is enabled.

Bit 5:

Output Low or Hi-Z. The LO/HIZ bit deter-

mines the state of the output during pow-

er-down. While the output is deactivated, if

the LO/HIZ bit is set to 0, the output will be

high impedance (high-Z). If the LO/HIZ bit is

set to 1, the output will be driven low.

Bit 4:

Reserved.

Bits 3 to 0:

Prescaler Divider. The prescaler bits (bits

P3 to P0) divide the master oscillator fre-

quency by 2x where x can be from 0 to

8. Any prescaler bit value entered that is

greater than 8 will decode as 8. See Table 1

for prescaler settings.

(+1, 2, 4,

OR 8% OF fMOSC)

PROGRAMMED

fMOSC

(-1, 2, 4,

OR 8% OF fMOSC)

IF DITHER AMOUNT = 0%

DITHER

AMOUNT

(2, 4, 8,

OR 16%)

1

fMOD

TIME

Figure 2. Output Frequency vs. Dither Rate

ADDR Register

Bits 7 to 6: Dither Percentage. The J3 and J2 bits con-

trol the selected dither amplitude (%). When

both J3 and J2 are set to 0, the default dith-

er rate is ±1%.

Bit 5:

Output Enable. The OE bit and the OE pin

state determine if the output is on when the

device is active (PDN = VIH). If (OE = 0 OR

OE is high) AND the PDN pin is high, the

output will be driven.

Bit 4:

Reserved.

Bit 3:

Write Control. The WC bit determines if

the EEPROM is to be written after register

contents have been changed. If WC = 0

(default), EEPROM is written automatically

after a write. If WC = 1, the EEPROM is

only written when the WRITE EE command

is issued. See the WRITE EE Command

section for more information.

Bits 2 to 0: Address. The A0, A1, A2 bits determine the

lower nibble of the I2C slave address.

Table 4. Register Summary

REGISTER

PRESCALER

ADDR BIT7

02h

J1

J0

LO/

HIZ

BINARY

X

P3 P2

BIT0

P1 P0

DEFAULT

xx00xxxxb

ACCESS

R/W

ADDR

0Dh

J3 J2 OE X WC A2 A1 A0

xx100000b

R/W

WRITE EE

3Fh

X = “don’t care”

x = values depend on custom settings

No Data

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