DS1089LU-21G View Datasheet(PDF) - Maxim Integrated
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DS1089LU-21G Datasheet PDF : 13 Pages
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DS1089L
3.3V Center Spread-Spectrum EconOscillator™
Output Control
Two user control signals control the output. The output
enable pin (OE) gates the output buffer and the pow-
er-down pin (PDN) disables the master oscillator and
turns off the output for power-sensitive applications.
(Note: the power-down command must persist for at least
two output frequency cycles plus 10µs for deglitching pur-
poses.) On power-up, the output is disabled until power is
stable and the master oscillator has generated 512 clock
cycles.
Additionally, the OE input is OR’ed with the OE bit in the
ADDR register, allowing for either hardware or software
gating of the output waveform (see the Block Diagram).
Both controls feature a synchronous enable, which
ensures that there are no output glitches when the output
is enabled. The synchronous enable also ensures a con-
stant time interval (for a given frequency setting) from an
enable signal to the first output transition.
Dither Generator
The DS1089L has the ability to reduce radiated emission
peaks. The output frequency can be dithered by ±1%,
±2%, ±4%, or ±8% symmetrically around the programmed
center frequency. Although the output frequency chang-
es when the dither is enabled, the duty cycle does not
change.
The dither rate (fMOD) is controlled by the J0 and J1
bits in the PRESCALER register and is enabled with the
SPRD pin. The maximum spectral attenuation occurs
when the prescaler is set to 1. The spectral attenuation is
reduced by 2.7dB for every factor of 2 that is used in the
prescaler. This happens because the prescaler’s divider
function tends to average the dither in creating the lower
frequency. However, the most stringent spectral emission
limits are imposed on the higher frequencies where the
prescaler is set to a low divider ratio.
A triangle-wave generator injects an offset element into
the master oscillator to dither its output. The dither rate
can be calculated based on the master oscillator frequen-
cy (see Equation 2).
Equation 2
f MOD
=
fMOSC
n
where fMOD = dither frequency, fMOSC = master oscillator
frequency, and n = divider setting (see Table 2).
Dither Percentage Settings
The dither amplitude (measured in percentage of the
master oscillator center frequency) is set using the J2
and J3 bits in the ADDR register. This circuit uses a sense
current from the master oscillator bias circuit to adjust the
amplitude of the triangle-wave signal to a voltage level
that modulates the master oscillator to a percentage of its
factory-programmed center frequency. This percentage is
set in the application to be ±1%, ±2%, ±4%, or ±8% (see
Table 3).
The location of bits P3, P2, P1, P0, J1, and J0 in the
PRESCALER register and bits J3 and J2 in the ADDR
register are shown in the Register Summary section.
Table 2. Dither Frequency Settings
BITS J1, J0
00
DITHER FREQUENCY
No dither
01
fMOSC/2048
10
fMOSC/4096
11
fMOSC/8192
Table 3. Dither Percentage Settings
BITS J3, J2
00
DITHER AMOUNT
±1%
01
±2%
10
±4%
11
±8%
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