DM9102H
Single Chip Fast Ethernet NIC Controller
3. Features
Integrated Fast Ethernet MAC, Physical Layer and
Transceiver in one chip.
Comply with PCI specification 2.2.
PCI clock up to 66MHz.
PCI bus master architecture.
PCI bus burst mode data transfer.
Two large independent transmission and receipt of
FIFO
Support transmit threshold under-run re-try mode
Up to 256K bytes Boot EPROM or Flash interface.
EEPROM 93C46 interface automatically supports node
ID load and configuration information.
Comply with IEEE 802.3u 100Base-TX and 802.3
10Base-T.
Comply with IEEE 802.3u auto-negotiation protocol for
automatic link type selection.
Support IEEE 802.3x Full Duplex Flow Control
VLAN frame length support.
IP/TCP/UDP checksum generation and checking
Comply with ACPI and PCI Bus Power Management.
Support the MII (Media Independent Interface) for an
external PHY
Support Wake-On-LAN function and remote wake-up
(Magic packet, Link Change and Microsoft® wake-up
frame).
Support 4 Wake-On-LAN (WOL) signals (active high
pulse, active low pulse, and active high, active low.)
High performance 100Mbps clock generator and data
recovery circuit.
Digital clock recovery circuit, using advanced digital
algorithm to reduce jitter.
Provides Loopback mode for easy system diagnostics.
Support auto-MDIX
+1.8/3.3V Power supply with +5V tolerant I/O.
128 pin LQFP with CMOS process.
Final
1
Version: DM9102H-12-DS-F01
February 15, 2008