CY7C4425-35AI View Datasheet(PDF) - Cypress Semiconductor
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CY7C4425-35AI Datasheet PDF : 25 Pages
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CY7C4425/4205/4215
CY7C4225/4235/4245
Depth Expansion Configuration
(with Programmable Flags)
The CY7C42X5 can easily be adapted to applications requir-
ing more than 64/256/512/1024/2048/4096 words of buffering.
Figure 2 shows Depth Expansion using three CY7C42X5s. Maxi-
mum depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
WXO RXO
VCC
FIRSTLOAD (FL)
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
FF
PAF
EF
PAE
WXI RXI
DATAIN (D)
WXO RXO
VCC
FIRSTLOAD (FL)
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
FF
PAF
EF
PAE
WXI RXI
DATAOUT (Q)
WRITECLOCK (WCLK)
WXO RXO
READ CLOCK (RCLK)
LOAD (LD)
WRITE ENABLE (WEN)
RESET (RS)
FF
PAF
7C4425
7C4205
7C4215
7C4225
7C4235
7C4235
FF
EF
PAFWXI RXIPAE
FIRSTLOAD (FL)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EF
PAE
42X5–23
Figure 2. Block Diagram of 192 x 18/768 x 18/1536 x 18/3072 x 18/12288 x 18 Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration.
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