CY7C4225-10AXI View Datasheet(PDF) - Cypress Semiconductor
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CY7C4225-10AXI Datasheet PDF : 25 Pages
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CY7C4205/CY7C4215
CY7C4225/CY7C4245
Switching Waveforms (continued)
Figure 8. First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
tDS
D0–D17
D0 (FIRSTVALID WRITE)
D1
D2
WEN
tENS
RCLK
tFRL[21]
tSKEW2
tREF
EF
D3
D4
REN
Q0–Q17
OE
WCLK
D0–D17
WEN
tDS
tENS
RCLK
EF
REN
OE
Q0–Q17
tOLZ
tA
tOE
Figure 9. Empty Flag Timing
D0
tENH
tFRL[21]
tSKEW2
tREF
tDS
tENS
tREF
tA
tA [22]
D0
D1
D1
tENH
tFRL[21]
tSKEW2
tREF
D0
Notes
21. WtSKhEeWn2t.STKEhWe 2La>temnicnyimTuimminsgpeacpipficlieastioonn,lytFaRtLt(hmeaExmimputymB) o=utnCdLaKr+y (tSEKFE=W2L.OWWh)e.n tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK +
22. The first word is available the cycle after EF goes HIGH, always.
Document Number: 001-45652 Rev. *B
Page 14 of 25
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