CY7C024-25JXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
View to exact match
CY7C024-25JXC
Cypress Semiconductor
CY7C024-25JXC Datasheet PDF : 21 Pages
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CY7C024/0241
CY7C025/0251
Switching Characteristics Over the Operating Range [13]
Parameter
Read Cycle
Description
7C024/0241–15 7C024/0241–25 7C024/0241–35 7C024/0241–55
7C025/0251–15 7C025/0251–25 7C025/0251–35 7C025/0251–55
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tRC
Read Cycle Time
15
25
35
55
ns
tAA
Address to Data Valid
15
25
35
55
ns
tOHA
Output Hold From Address
3
3
3
3
ns
Change
tACE[14]
CE LOW to Data Valid
15
25
35
55
ns
tDOE
OE LOW to Data Valid
10
13
20
25
ns
tLZOE[15, 16, 17] OE Low to Low Z
3
3
3
3
ns
tHZOE[15, 16, 17] OE HIGH to High Z
10
15
20
25
ns
tLZCE[15, 16, 17] CE LOW to Low Z
3
3
3
3
ns
tHZCE[15, 16, 17] CE HIGH to High Z
10
15
20
25
ns
tPU[17]
CE LOW to Power-Up
0
0
0
0
ns
tPD[17]
CE HIGH to Power-Down
15
25
25
55
ns
tABE[14]
Byte Enable Access Time
15
25
35
55
ns
Write Cycle
tWC
Write Cycle Time
15
25
35
55
ns
tSCE[14]
CE LOW to Write End
12
20
30
35
ns
tAW
Address Set-Up to Write End 12
20
30
35
ns
tHA
Address Hold From Write
0
0
0
0
ns
End
tSA[14]
Address Set-up to Write Start 0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
35
ns
tSD
Data Set-Up to Write End
10
15
15
20
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[16, 17] R/W LOW to High Z
10
15
20
25
ns
tLZWE[16, 17] R/W HIGH to Low Z
0
0
0
0
ns
tWDD[18]
Write Pulse to Data Delay
30
50
60
70
ns
tDDD[18]
Write Data Valid to Read
Data Valid
25
35
35
45
ns
Notes:
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
14. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
15. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
16. Test conditions used are Load 3.
17. This parameter is guaranteed but not tested.
18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document #: 38-06035 Rev. *C
Page 9 of 21
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