CY7C008V View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
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CY7C008V Datasheet PDF : 18 Pages
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CY7C008V/009V
CY7C018V/019V
Switching Characteristics Over the Operating Range[10]
CY7C008V/009V
CY7C018V/019V
-15
-20
-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
tACE[11]
Output Hold From Address Change
CE LOW to Data Valid
tDOE
tLZOE[12, 13, 14]
tHZOE[12, 13, 14]
tLZCE[12, 13, 14]
tHZCE[12, 13, 14]
tPU[14]
tPD[14]
tABE[11]
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable Access Time
WRITE CYCLE
15
20
25
ns
15
20
25
ns
3
3
3
ns
15
20
25
ns
10
12
13
ns
3
3
3
ns
10
12
15
ns
3
3
3
ns
10
12
15
ns
0
0
0
ns
15
20
25
ns
15
20
25
ns
tWC
tSCE[11]
Write Cycle Time
CE LOW to Write End
tAW
Address Valid to Write End
tHA
tSA[11]
Address Hold From Write End
Address Set-Up to Write Start
tPWE
Write Pulse Width
tSD
Data Set-Up to Write End
tHD
Data Hold From Write End
tHZWE[13, 14]
R/W LOW to High Z
tLZWE[13, 14]
R/W HIGH to Low Z
tWDD[15]
Write Pulse to Data Delay
tDDD[15]
Write Data Valid to Read Data Valid
BUSY TIMING[16]
15
20
25
ns
12
16
20
ns
12
16
20
ns
0
0
0
ns
0
0
0
ns
12
17
22
ns
10
12
15
ns
0
0
0
ns
10
12
15
ns
3
3
3
ns
30
40
50
ns
25
30
35
ns
tBLA
BUSY LOW from Address Match
15
20
20
ns
tBHA
BUSY HIGH from Address Mismatch
15
20
20
ns
tBLC
BUSY LOW from CE LOW
15
20
20
ns
tBHC
BUSY HIGH from CE HIGH
15
16
17
ns
tPS
Port Set-Up for Priority
5
5
5
ns
tWB
R/W HIGH after BUSY (Slave)
0
0
0
ns
Notes:
10. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOI/IOH and 30-pF load capacitance.
11. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
12. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
13. Test conditions used are Load 2.
14. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port,
refer to Read Timing with Busy waveform.
15. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
16. Test conditions used are Load 1.
Document #: 38-06044 Rev. *C
Page 6 of 18
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