CY7C008V(2010) View Datasheet(PDF) - Cypress Semiconductor
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Description
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CY7C008V Datasheet PDF : 23 Pages
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CY7C008V/009V
CY7C018V/019V
Functional Description
The CY7C008V/009V and CY7C018V/019V are low-power
CMOS 64 K, 128 K × 8/9 dual-port static RAMs. Various
arbitration schemes are included on the devices to handle
situations when multiple processors access the same piece of
data. Two ports are provided permitting independent,
asynchronous access for reads and writes to any location in
memory. The devices can be utilized as standalone 8/9-bit
dual-port static RAMs or multiple devices can be combined in
order to function as a 16/18-bit or wider master/slave dual-port
static RAM. An M/S pin is provided for implementing 16/18-bit or
wider memory applications without the need for separate master
and slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE), read
or write enable (R/W), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the
port is trying to access the same location currently being
accessed by the other port. The interrupt flag (INT) permits
communication between ports or systems by means of a mail
box. The semaphores are used to pass a flag, or token, from one
port to the other to indicate that a shared resource is in use. The
semaphore logic is comprised of eight shared latches. Only one
side can control the latch (semaphore) at any time. Control of a
semaphore indicates that a shared resource is in use. An
automatic power-down feature is controlled independently on
each port by a chip select (CE) pin.
The CY7C008V/009V and CY7C018V/019V are available in
100-pin Thin Quad Plastic Flatpacks (TQFP).
Document Number: 38-06044 Rev. *E
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