CY7C144AV(2011) View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
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CY7C144AV Datasheet PDF : 21 Pages
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CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 8K/16K x 8
Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow
simultaneous access of the same memory location
■ 8K/16K x 8 organizations
(CY7C144AV/006AV)
■ 0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
■ High-speed access: 25 ns
■ Low operating power
— Active: ICC = 115 mA (typical)
— Standby: ISB3 = 10 A (typical)
■ Fully asynchronous operation
■ Automatic power-down
Logic Block Diagram
R/WL
CEL
OEL
[1]
8
I/O0L–I/O7L
I/O
Control
CY7C144AV
CY7C006AV
3.3V 8K/16K x 8
Dual-Port Static RAM
■ Expandable data bus to 16 bits or more using Master/ Slave
chip select when using more than one device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flag for port-to-port communication
■ Pin select for Master or Slave
■ Commercial and industrial temperature ranges
■ Available in 64-pin thin quad flat pack (TQFP) (7C006AV &
7C144AV)
■ Pb-free packages available
I/O
Control
R/WR
CER
OER
8
[1]
I/O0R–I/O7R
A0L–A[122] –13L
13–14
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
13–14
[2]
A0R–A12–13R
A0L–A[122] –13L
CEL
OEL
R/WL
SEML
BUSYL [3]
INTL
13–14
Notes
1. I/O0–I/O7 for x8 devices
2. A0–A12 for 8K devices; A0–A13 for 16K devices
3. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
13–14
A0R–A1[22]–13R
CER
OER
R/WR
SEMR
[3]BUSYR
INTR
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-06051 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 4, 2011
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