CS5509(1995) View Datasheet(PDF) - Cirrus Logic
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Description
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CS5509 Datasheet PDF : 30 Pages
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CS5509
5V SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = 5V ± 10%; Input Levels:
Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol Min
Typ
Max
Units
Master Clock Frequency Internal Oscillator:
External Clock:
XIN
30.0
32.768
53.0
kHz
fclk
30
-
330
kHz
Master Clock Duty Cycle
40
-
60
%
Rise Times:
Any Digital Input (Note 10) trise
-
Any Digital Output
-
-
1.0
µs
50
-
ns
Fall Times:
Any Digital Input (Note 10) tfall
-
Any Digital Output
-
-
1.0
µs
20
-
ns
Start-Up
Power-On Reset Period
(Note 11) tres
-
10
-
ms
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu
-
500
-
ms
Wake-up Period
(Note 13) twup
-
1800/fclk
-
s
Calibration
CONV Pulse Width (CAL=1)
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration
(Note 14) tccw
tscl
tcal
100
-
-
ns
-
-
2/fclk+200
ns
-
3246/fclk
-
s
Conversion
CONV Pulse Width
tcpw
100
-
-
ns
CONV High to Start of Conversion
tscn
-
-
2/fclk+200
ns
Set Up Time
BP/UP stable prior to DRDY
tbus
82/fclk
-
-
s
falling
Hold Time
BP/UP stable after DRDY falls tbuh
0
-
-
ns
Start of Conversion to End of Conversion
(Note 15) tcon
-
1624/fclk
-
s
Notes: 10. Specified using 10% and 90% points on waveform of interest.
11. An internal power-on-reset is activated whenever power is applied to the device.
12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when
using an external clock source.
13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the
power-on reset time elapses.
14. Calibration can also be initiated by pulsing CAL high while CONV=1.
15. Conversion time will be 1622/fclk if CONV remains high continuously.
4
DS125F1
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