CS51411 View Datasheet(PDF) - ON Semiconductor
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CS51411 Datasheet PDF : 20 Pages
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CS51411, CS51412, CS51413, CS51414
APPLICATIONS INFORMATION
THEORY OF OPERATION
V2 Control
The CS5141X family of buck regulators utilizes a V2
control technique and provides a high level of integration to
enable high power density design optimization.
Every pulse width modulated controller configures basic
control elements such that when connected to the feedback
signal of a power converter, sufficient loop gain and
bandwidth is available to regulate the voltage set point
against line and load variations. The arrangement of these
elements differentiates a voltage mode, or a current mode
controller from a V2 device.
Figure 3 illustrates the basic architecture of a V2
controller.
Latch/Drive
Switch
PWM
Error Amplifier
-
+
Z2 VREF
VFB Z1 VO
Clock
V2 Control Ramp
Figure 3. V2 Control
In common with V mode or I mode, the feedback signal
is compared with a reference voltage to develop an error
signal which is fed to one input of the PWM. The second
input to the PWM, however, is neither a fixed voltage ramp
nor the switch current, but rather the feedback signal from
the output of the converter. This feedback signal provides
both DC information as well as AC information (the control
ramp) for the converter to regulate its set point. The control
architecture is known as V2 since both PWM inputs are
derived from the converter's output voltage. This is a little
misleading because the control ramp is typically generated
from current information present in the converter.
The feedback signal from the buck converter shown in
Figure 4 is processed in one of two ways before being routed
to the inputs of the PWM comparator. The Fast Feedback
path (FFB) adds slope compensation to the feedback signal
before passing it to one input of the PWM. The Slow
Feedback path (SFB) compares the original feedback signal
against a DC reference. The error signal generated at the
output of the error amplifier VC is filtered by a low
frequency pole before being routed to the second input of the
PWM. Each switch cycle is initiated (S1 on), when the
output latch is set by the oscillator. Each switch cycle
terminates (S1 off), when the FFB signal (AC plus output
DC) exceeds SFB (error DC), and the output latch is reset.
In the event of a load transient, the FFB signal changes
faster, in relation to the filtered SFB signal, causing duty
cycle modulation to occur. Actual oscilloscope waveforms
taken from the converter show the switch node VSWITCH,
the error signal VC and the feedback signal VFB (AC
component only) are shown in Figure 5.
S1
L1
VIN
Duty Cycle
D1
VO
R1
C1
Buck
Controller
Slope
Oscillator Comp
FFB
Latch
R
S
PWM Com‐
parator
V2 Control
SFB
VC
Error
Amplifier
R2
VREF
+
-
Figure 4. Buck Converter with V2 Control
VSWITCH
VC
VFB
Figure 5.
In the event of a load transient, the FFB signal changes
faster, in relation to the filtered SFB signal, causing duty
cycle modulation to occur. By this means the converter's
transient response time is independent of the error amplifier
bandwidth. The error amplifier is used here to ensure
excellent DC accuracy.
In order for the controller to operate optimally, a stable
ramp is required at the feedback pin.
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