CS5150HGD16 View Datasheet(PDF) - Cherry semiconductor

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CS5150HGD16

High Performance/ Integrated Current Mode PWM Controllers

Cherry semiconductor 

Applications Information: continued

If the input voltage rises quickly, or the regulator output is

enabled externally, output voltage will increase to the level

set by the error amplifier output more rapidly, usually

within a couple of cycles (see Figure 4).

Trace1 - Regulator Output Voltage (10V/div.)

Trace 2 - Inductor Switching Node (5V/div.)

Figure 6: Peak-to-peak ripple on VOUT = 2.8V, IOUT = 13A (heavy load).

Trace 1 - Regulator Output Voltage (5V/div.)

Trace 2 - Inductor Switching Node (5V/div.)

Figure 4: CS5150H demonstration board enable startup waveforms.

Normal Operation

During normal operation, switch off time is constant and

set by the COFF capacitor. Switch on time is adjusted by the

V2™ control loop to maintain regulation. This results in

changes in regulator switching frequency, duty cycle, and

output ripple in response to changes in load and line.

Output voltage ripple will be determined by inductor rip-

ple current working into the ESR of the output capacitors

(see Figures 5 and 6).

Trace 1 - Regulator Output Voltage (10V/div.)

Trace 2 - Inductor Switching Node (5V/div.)

Figure 5: Peak-to-peak ripple on VOUT = 2.8V, IOUT = 0.5A (light load).

Transient Response

The CS5150H V2™ control loop’s 100ns reaction time pro-

vides unprecedented transient response to changes in

input voltage or output current. Pulse by pulse adjustment

of duty cycle is provided to quickly ramp the inductor cur-

rent to the required level. Since the inductor current cannot

be changed instantaneously, regulation is maintained by

the output capacitor(s) during the time required to slew the

inductor current.

Overall load transient response is further improved

through a feature called “adaptive voltage positioning”.

This technique pre-positions the output capacitor’s voltage

to reduce total output voltage excursions during changes

in load.

Holding tolerance to 1% allows the error amplifier’s refer-

ence voltage to be targeted +40mV high without compro-

mising DC accuracy. A “droop resistor“, implemented

through a PC board trace, connects the error amplifier’s

feedback pin (VFB) to the output capacitors and load and

carries the output current. With no load, there is no DC

drop across this resistor, producing an output voltage

tracking the error amplifier’s, including the +40mV offset.

When the full load current is delivered, an 80mV drop is

developed across this resistor. This results in output volt-

age being offset -40mV low.

The result of adaptive voltage positioning is that additional

margin is provided for a load transient before reaching the

output voltage specification limits. When load current sud-

denly increases from its minimum level, the output capaci-

tor is pre-positioned +40mV. Conversely, when load cur-

rent suddenly decreases from its maximum level, the out-

put capacitor is pre-positioned -40mV (see Figures 7, 8, and

9). For best transient response, a combination of a number

of high frequency and bulk output capacitors are usually

used.

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