74LVT16500A(2006) View Datasheet(PDF) - Philips Electronics
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74LVT16500A Datasheet PDF : 19 Pages
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Philips Semiconductors
74LVT16500A
3.3 V 18-bit universal bus transceiver; 3-state
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
∆ICC
additional quiescent supply per input pin; VCC = 3 V to 3.6 V; one input [7] -
current
at VCC − 0.6 V; other inputs at VCC or GND
Ci
input capacitance
control pins; VI = 0 V or 3.0 V
-
Cio
input/output capacitance
I/O pins; VI/O = 0 V or 3.0 V
-
Typ Max Unit
0.1 0.2 mA
3
-
pF
9
-
pF
[1] Typical values are at VCC = 3.3 V and Tamb = 25 °C.
[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.0 V ± 0.3 V
a transition time of 100 µs is permitted. This parameter is valid for Tamb = 25 °C only.
[6] ICC is measured with outputs pulled to VCC or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.7 V; Tamb = −40 °C to 85 °C
tPLH
propagation delay
An to Bn or Bn to An
see Figure 5
-
-
5.4
ns
CPAB to Bn or CPBA to An
see Figure 6
-
-
6.4
ns
LEAB to Bn or LEBA to An
see Figure 7
-
-
6.4
ns
tPHL
propagation delay
An to Bn or Bn to An
see Figure 5
-
-
5.4
ns
CPAB to Bn or CPBA to An
see Figure 6
-
-
6.4
ns
LEAB to Bn or LEBA to An
see Figure 7
-
-
6.4
ns
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
output enable time to HIGH-level see Figure 8
output enable time to LOW-level see Figure 9
output disable time from HIGH-level see Figure 8
output disable time from LOW-level see Figure 9
setup time HIGH
An to CPAB or Bn to CPBA
see Figure 10
-
-
-
-
-
-
-
-
2.5
-
5.5
ns
5.2
ns
6.3
ns
5.6
ns
-
ns
An to LEAB with CPAB LOW or see Figure 10
2.2
-
-
ns
Bn to LEBA with CPBA LOW
An to LEAB with CPAB HIGH or see Figure 10
2.7
-
-
ns
Bn to LEBA with CPBA HIGH
74LVT16500A_3
Product data sheet
Rev. 03 — 29 May 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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