Bt8110/8110B
High-Capacity ADPCM Processor
3.0 Registers
3.2 0x40—Mode Control Register (mode)
Table 3-2. Bt8110B Internal Lookup Table ROM (2 of 2)
CODE[3:0]
Internal ROM Code Table
1100
1101
1110
1111
G.727 (5,5)—Embedded Code
G.727 (x,4)—Embedded Code
G.727 (x,3)—Embedded Code
G.727 (x,2)—Embedded Code
3.2 0x40—Mode Control Register (mode)
A write to address 0x40 will address the mode control registers for all 24 or 32 channels. Five bits are used to
control the mode of operation of the Bt8110/8110B. This register is write-only.
6
RSVD
RSVD
EN_FRMR
EN_32CH
MODE[2:0]
5
RSVD
4
EN_FRMR
3
EN_32CH
2
MODE[2]
1
MODE[1]
0
MODE[0]
Reserved—Unused; should be set to a logic low.
Enable Direct T1/E1 Framer Interface—Set for direct connection to a T1 or E1 framer circuit.
Enable 32-Channel Operation—Set for 32-channel full duplex or 64-channel half-duplex
operation. If it is not set, 24-channel full-duplex or 48-channel half-duplex operation is
obtained.
Mode Control—Set to the values required to obtain the desired operating mode configuration
as follows:
Bit 2
Bit 1
Bit 0
Source
1
0
0
1
0
1
1
1
0
1
1
1
Interleaved
Encoder
Decoder
Not Used
100060C
Conexant
3-3