AN601 View Datasheet(PDF) - Vishay Semiconductors

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AN601

Unclamped Inductive Switching Rugged MOSFETs For Rugged Environments

Vishay Semiconductors 

AN601

Vishay Siliconix

L

I

D.U.T.

+

VDD

–

V(BR)eff

V(BR)DSS

IO

VDD

FIGURE 1. UIS Test Circuit

The classic UIS test circuit in widespread use* is shown in

Figure 1. Using this circuit, the energy absorbed by the power

MOSFET may be calculated using

ƪ ƫ E + 1ń2 lo2L

V(BR) eff

V(BR) eff – VDD

(2)

An alternate circuit removes VDD (i.e., VDD = 0) just prior to

switching the device off, thus eliminating the last term in

equation (2).

Reviewing the switching waveform shown in Figure 2, the

gate remains on long enough to ramp the current to IO, at which

time the gate switches off, resulting in an abrupt break in the

drain current. Since the magnetic field of the inductor cannot

instantaneously collapse, a voltage is induced on the drain of

the MOSFET in accordance with equation (1). This induced

potential may easily exceed the (avalanche) breakdown

voltage shown on the data sheet.** During avalanche, the

voltage is clamped at a value of V(BR)eff, and the current stored

in the inductor decays linearly from IO to zero. This decay time

may be determined by rearranging equation (1).

L lo

tAV + V(BR) eff

(3)

0

tav

FIGURE 2. UIS Waveform during Switching

Theories Pertaining to Stress Failures

The Bipolar Excitation Effect –– The “Active” Mode. The

classic reason for failure when a MOSFET is stressed focuses

on the activation and subsequent secondary breakdown of the

parasitic bipolar transistor. The intrinsic diode of a DMOS FET

is actually the collector-base junction of this parasitic

transistor. Whether the stress is a form of dv/dt[2,3] or UIS,

current cascading laterally through the p+ region is considered

responsible for transistor failure when the voltage drop, IORp+,

activates this bipolar transistor.[4,5,6] The accepted model

representing this failure mode in the vertical MOSFET

structure is offered in Figure 3.

The initial avalanche current at breakdown is heavily

concentrated within the MOSFET’s inherent Zener diode

(afforded by the deep p+ well situated centrally in each cell, as

shown in Figure 3). However, as the avalanche current

continues to increase, it also spreads across the p/n barrier.

The lateral resistance (Rp) is much greater than the “vertical”

resistance (RB) of the heavily-doped p+ region. Avalanche

current concentrated in the p+ (Zener) region does not

normally initiate bipolar action. As the avalanche current

increases in intensity, it spreads along the p/n barrier, and the

scenario follows the classic reasoning. If the avalanche

currents cascading laterally through the p-doped region

(pseudobase region) develop sufficient forward bias across Rp

to offset VBE, the normal forward base current, +IB, in

conjunction with the beta of the parasitic npn bipolar transistor,

will result in a local breakdown voltage equal to BVCEO (which

is approximately half of V(BR)DSS). The resulting mesoplasma

causes thermal runaway and the destruction of the power

MOSFET.

*Recommended by JEDEC Committee JC–25.

**Avalanche breakdown, V(BR)DSS, offered in the typical data sheet is generally rated at the zero gate voltage drain current (IDSS) of the MOSFET.

Avalanche breakdown during UIS (V(BR)eff) is, as shown in Figure 2, at substantially higher drain currents. V(BR)eff is much greater than

V(BR)DSS.

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Document Number: 70572

15-Feb-94

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