MH4V64AXJJ View Datasheet(PDF) - MITSUBISHI ELECTRIC
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MH4V64AXJJ Datasheet PDF : 25 Pages
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Preliminary
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MITSUBISHI LSIs
MH4V64/644AXJJ-5,-6,-5S,-6S
FAST PAGE MODE 268435456-BIT (4194304-WORD BY 64-BIT)DYNAMIC RAM
SWITCHING CHARACTERISTICS (Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,13,14)
Symbol
Parameter
Limits
-5,-5S
-6,-6S
Unit
Min Max Min Max
tCAC Access time from /CAS
(Note 7,8)
13
15
ns
tRAC Access time from /RAS
(Note 7,9)
50
60
ns
tAA
Column address access time
(Note 7,10)
25
30
ns
tCPA Access time from /CAS precharge
(Note 7,11)
30
35
ns
tOEA Access time from /OE
(Note 7)
13
15
ns
tCLZ Output low impedance time from /CAS low (Note 7) 5
5
ns
tOFF Output disable time after /CAS high
(Note 12) 0 13
0 15
ns
tOEZ Output disable time after /OE high
(Note 12) 0 13
0 15
ns
Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a /RAS clock such as /RAS-Only refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) loads and 100pF. The reference levels for
measuring of output signals are 2.0(VOH)and 0.8(VOL).
8: Assumes that tRCD≥tRCD(max), tASC≥tASC(max) and tCP≥tCP(max).
9: Assumes that tRCD≤tRCD(max) and tRAD≤tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in
this table,tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD≥tRAD(max) and tASC≤tASC(max).
11: Assumes that tCP≤tCP(max) and tASC≥tASC(max).
12: tOFF(max) and tOEZ(max) defines the time at which the output achieves the high impedance state (IOUT≤ I ±10uAI) and
is not reference to VOH(min) or VOL(max).
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 13,14)
Limits
Symbol
Parameter
-5,-5S
-6,-6S
Unit
Min Max Min Max
tREF Refresh cycle time
64
64 ms
tRP
/RAS high pulse width
30
40
ns
tRCD Delay time, /RAS low to /CAS low
(Note15) 18 37 20 45
ns
tCRP Delay time, /CAS high to /RAS low
5
10
ns
tRPC Delay time, /RAS high to /CAS low
0
0
ns
tCPN /CAS high pulse width
10
10
ns
tRAD Column address delay time from /RAS low (Note16) 13 25 15 30
ns
tASR Row address setup time before /RAS low
0
0
ns
tASC Column address setup time before /CAS low (Note17) 0
5
0 10
ns
tRAH Row address hold time after /RAS low
8
10
ns
tCAH Column address hold time after /CAS low
13
15
ns
tDZC Delay time, data to /CAS low
(Note18) 0
0
ns
tDZO Delay time, data to /OE low
tCDD Delay time, /CAS high to data
(Note18) 0
0
ns
(Note19) 13
15
ns
tODD Delay time, /OE high to data
(Note19) 13
15
ns
tT
Transition time
(Note20) 1 50
1 50
ns
Note 13: The timing requirements are assumed tT =5ns.
14: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.VIH(min) and VIL(max) of the switching characteristics
are 2.0V and 0.8V respectively.
15: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than
tRCD(max), access time is controlled exclusively by tCAC or tAA.tRCD(min) is specified as tRCD(min)=tRAH(min)+2tT+tASC(min) .
16: tRAD(max) is specified as a reference point only. If tRAD≥tRAD(max) and tASC≤tASC(max), access time is controlled exclusively by tAA.
17: tASC(max) is specified as a reference point only. If tRCD≥tRCD(max) and tASC≥tASC(max), access time is controlled exclusively by
tCAC.
18: Either tDZC or tDZO must be satisfied.
19: Either tCDD or tODD must be satisfied.
20: tT is measured between VIH(min) and VIL(max).
MIT-DS-0072-0.5
MITSUBISHI
ELECTRIC
( 11 / 25 )
26/Feb./1997
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