AGM1264M View Datasheet(PDF) - AZ Displays
Part Name
Description
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AGM1264M Datasheet PDF : 13 Pages
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3. I/O Terminals
3.1 Pin Description
Pin NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-23
24
25
26
27
28
Symbol Function Description
PS
Parallel or Serial data input select
C86
MPU Interface select(6800 or 8080)
V0
LCD driver supply voltage
V4
LCD driver supply voltage
V3
LCD driver supply voltage
V2
LCD driver supply voltage
V1
LCD driver supply voltage
C2-
For internal DC/DC voltage converter
C2+
For internal DC/DC voltage converter
C1+
For internal DC/DC voltage converter
C1-
For internal DC/DC voltage converter
C3+
For internal DC/DC voltage converter
VOUT DC/DC voltage converter output
VSS Logic Ground.
VDD Logic supply voltage.
DB7-DB0
Quasi-Bidirectional I/O Data Bus.
Three state I/O common terminal.
DB0 (LSB) ... DB7 (MSB)
/RD(E)
When connected to an 8080 MPU, it is active LOW. This pad is
connected to the RD signal of the 8080MPU, and the NT7532 data bus
is in an output status when this signal is "L" When connected to a 6800
Series MPU, this is active HIGH. This is used as an enable clock input
of the 6800 series MPU
/WR(R/W
When connected to an 8080 MPU, this is active LOW. This terminal
connects to the 8080 MPU WR signal. The signals on the data bus are
latched at the rising edge of the WR signal. When connected to a 6800
Series MPU, this is the read/write control signal input terminal.
When W R/ = "H": Read
When W R/ = "L": Write
Data or Instruction.
A0
A0 = H DB<0:7>: Display RAM data
A0 = L DB<0:7>: Instruction data
/RES
/CS1
14 16 RES I When RES is set to "L", the settings are initialized. The
reset operation is performed by the RES signal level
This is the chip select signal. When CS1="L", then the chip select
becomes active, and data/command I/O is enabled.
AZ DISPLAYS, INC.
4
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