ADT7410 View Datasheet(PDF) - Analog Devices
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ADT7410 Datasheet PDF : 24 Pages
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ADT7410
I2C TIMING SPECIFICATIONS
TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns
(10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
SERIAL INTERFACE1, 2
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Setup Time (Start Condition), tSU;STA
Data Setup Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Condition), tBUF
Min Typ Max
0
400
0.6
1.3
0.3
0.3
0.6
0.6
0.25
0.35
0.6
0
1.3
Unit
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
Test Conditions/Comments
See Figure 2
After this period, the first clock is generated
Relevant for repeated start condition
VDD ≥ 3.0 V
VDD < 3.0 V
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
Timing Diagram
tLOW tR
SCL
tHD:STA
tHD:DAT
SDA
tBUF
P
S
tF
tHIGH
tSU:DAT
tHD:STA
tSU:STA
S
Figure 2. Serial Interface Timing Diagram
tSU:STO
P
Rev. 0 | Page 4 of 24
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