ADNS-5030 View Datasheet(PDF) - Avago Technologies
Part Name
Description
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ADNS-5030 Datasheet PDF : 24 Pages
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SENSOR
LENS
Z
=
2.40
(0.094)
OBJECT SURFACE
LENS REFERENCE PLANE
Figure 9. Distance from lens reference plane to tracking surface (Z).
AC Electrical Specifications
Electrical Characteristics over recommended operating conditions. Typical values at 25 °C, VDD = 3.3 V.
Parameter
Symbol Minimum Typical MaximumUnits Notes
Reset Pulse Width
tRESET
250
ns
Motion Delay after Reset
tMOT-RST
50
ms
Forced Rest Enable
tREST-EN
1
s
Wake from Forced Rest
tREST-DIS
1
s
Power Down
tPD
50
ms
Active low
From NRESET pull high to valid motion, assuming
VDD and motion is present
From Rest Mode(RM) bits set to target rest mode
From Rest Mode(RM) bits cleared to valid motion
From PD (when bit 1 of register 0x0d is set) to
low current
Wake from Power Down
tWAKEUP 50
55
ms
From PD inactive (when NRESET pin is asserted low to
high or write 0x5a to register 0x3a) to valid motion
MISO Rise Time
tr-MISO
40
200
ns
MISO Fall Time
tf-MISO
40
200
ns
MISO Delay after SCLK
tDLY-MISO
120
ns
CL = 100 pF
CL = 100 pF
From SCLK falling edge to MISO data valid, no load
conditions
MISO Hold Time
thold-MISO 0.5
1/fSCLK
µs
MOSI Hold Time
thold-MOSI 200
ns
MOSI Setup Time
tsetup-MOSI 120
ns
SPI Time between Write
tSWW
30
µs
Commands
Data held until next falling SCLK edge
Amount of time data is valid after SCLK rising edge
From data valid to SCLK rising edge
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second data byte
SPI Time between Write and tSWR
20
µs
Read Commands
From rising SCLK for last bit of the first data byte,
to rising SCLK for last bit of the second address byte
SPI Time between Read
tSRW
250
ns
and Subsequent Commands tSRR
SPI Read Address-Data
tSRAD
4
µs
Delay
From rising SCLK for last bit of the first data byte, to
falling SCLK for the first bit of the next address
From rising SCLK for last bit of the address byte,
to falling SCLK for first bit of data being read
NCS Inactive after Motion tBEXIT
250
ns
Burst
Minimum NCS inactive time after motion burst before
next SPI usage
NCS to SCLK Active
tNCS-SCLK 120
ns
SCLK to NCS Inactive
tSCLK-NCS 120
ns
(for Read Operation)
From NCS falling edge to first SCLK rising edge
From last SCLK rising edge to NCS rising edge,
for valid MISO data transfer
SCLK to NCS Inactive
tSCLK-NCS 20
µs
(for Write Operation)
From last SCLK rising edge to NCS rising edge,
for valid MOSI data transfer
NCS to MISO high-Z
tNCS-MISO
250
ns
From NCS rising edge to MISO high-Z state
Transient Supply Current IDDT
60
mA Max supply current during a VDD ramp from 0 to VDD
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