ADN2815ACPZ-500RL7(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
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ADN2815ACPZ-500RL7
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADN2815ACPZ-500RL7 Datasheet PDF : 24 Pages
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ADN2815
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Transfer BW
Jitter Peaking
Jitter Generation
Conditions
OC-12
OC-3
OC-12
OC-3
OC-12, 12 kHz to 5 MHz
OC-3, 12 kHz to 1.3 MHz
Min
Typ
Max
75
26
0
0
0.001
0.011
0.001
0.005
130
42
0.03
0.03
0.003
0.026
0.002
0.010
Unit
kHz
kHz
dB
dB
UI rms
UI p-p
UI rms
UI p-p
Jitter Tolerance
GbE, IEEE 802.3
637 kHz
OC-12, 223 − 1 PRBS
30 Hz1
300 Hz1
25 kHz
250 kHz1
OC-3, 223 − 1 PRBS
30 Hz1
300 Hz1
6500 Hz
65 kHz1
0.749
100
44
2.5
1.0
50
24
3.5
1.0
1 Jitter tolerance of the ADN2815 at these jitter frequencies is better than what the test equipment is able to measure.
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
Rev. 0 | Page 4 of 24
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