ADF4193 View Datasheet(PDF) - Analog Devices
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ADF4193 Datasheet PDF : 32 Pages
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ADF4193
POWER-DOWN REGISTER (R5)
PD
DIFF AMP
CONTROL
BITS
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3 DB2 DB1 DB0
F1 C3 (1) C2 (0) C1 (1)
Data Sheet
F1 COUNTER RESET
0 NORMAL OPERATION
1 COUNTER RESET
CHARGE PUMP
F2 3-STATE
0 NORMAL OPERATION
1 3-STATE ENABLED
CHARGE PUMP
F3 POWER-DOWN
0 DISABLED
1 ENABLED
DIFF AMP
F5 F4 POWER-DOWN
0 0 DISABLED
1 1 ENABLED
Figure 34. Power-Down Register (R5)
R5, the power-down register (C3, C2, C1 set to 1, 0, 1, respectively)
can be used to software power down the PLL and differential
amplifier sections. After power is initially applied, there must be
writes to R5 to clear the power-down bits and to R2, R1, and R0
before the ADF4193 comes out of power-down.
Power-Down Differential Amplifier
When Bit DB6 and Bit DB7 are set high, the differential
amplifier is put into power-down. When Bit DB6 and Bit DB7
are set low, normal operation is resumed.
Power-Down Charge Pump
Setting Bit DB5 high activates a charge pump power-down and
the following events occur:
• All active dc current paths are removed, except for the
differential amplifier.
For normal operation, Bit DB5 should be set to 0, followed by a
write to R0.
CP Three-State
When this bit is set high, the charge pump outputs are put into
three-state. With the bit set low, the charge pump outputs are
enabled.
Counter Reset
When this bit is set to 1, the counters are held in reset. For normal
operation, this bit should be 0, followed by a write to R0.
• The R and N divider counters are forced to their load state
conditions.
• The charge pump is powered down with its outputs in three-
state mode.
• The digital lock detect circuitry is reset.
• The RFIN input is debiased.
• The reference input buffer circuitry is disabled.
• The serial interface remains active and capable of loading and
latching data.
Rev. F | Page 20 of 32
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