EV-ADF4157SD1Z View Datasheet(PDF) - Analog Devices
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EV-ADF4157SD1Z Datasheet PDF : 24 Pages
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ADF4157
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
RF INT Divider............................................................................. 9
25-Bit Fixed Modulus .................................................................. 9
INT, FRAC, and R Relationship ................................................. 9
RF R Counter ................................................................................ 9
Phase Frequency Detector (PFD) and Charge Pump............ 10
MUXOUT and Lock Detect...................................................... 10
Input Shift Register..................................................................... 10
REVISION HISTORY
8/12—Rev. C to Rev. D
Changes to Figure 4 and Table 5......................................................6
Updated Outline Dimensions (Changed CP-20-1 to CP-20-6) .....22
Changes to Ordering Guide ...........................................................21
Criticizing
3/12—Rev. B to Rev. C
Changes to Table 1............................................................................ 3
Changes to Ordering Guide .......................................................... 21
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................ 3
Changes to EPAD Note .................................................................... 6
1/09—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Reference Characteristics Parameter, Table 1 .......... 3
Changes to Table 3............................................................................ 5
Data Sheet
Program Modes .......................................................................... 10
Register Maps.................................................................................. 11
FRAC/INT Register (R0) Map.................................................. 12
LSB FRAC Register (R1) Map .................................................. 13
R Divider Register (R2) Map .................................................... 14
Function Register (R3) Map ..................................................... 16
Test Register (R4) Map .............................................................. 17
Applications Information .............................................................. 18
Initialization Sequence .............................................................. 18
RF Synthesizer: A Worked Example ........................................ 18
Reference Doubler and Reference Divider ............................. 18
Cycle Slip Reduction for Faster Lock Times........................... 18
Fastlock Timer and Register Sequences .................................. 19
Fastlock: An Example ................................................................ 19
Fastlock: Loop Filter Topology ................................................. 19
Spur Mechanisms ....................................................................... 19
Low Frequency Applications .................................................... 20
Filter Design—ADIsimPLL....................................................... 20
Operating with Wide Loop Filter Bandwidths....................... 20
PCB Design Guidelines for the Chip Scale Package.............. 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
Changes to Figure 4 and Table 5......................................................6
Changes to Figure 15...................................................................... 10
Changes to Figure 16...................................................................... 11
Changes to Figure 17...................................................................... 12
Changes to Figure 19...................................................................... 15
Added Negative Bleed Current Section, CLK Divider Mode
Section, and 12-Bit Clock Divider Value Section....................... 17
Changes to Reserved Bits Section and Figure 21 ....................... 17
Deleted Interfacing Section........................................................... 18
Added Fastlock Timer and Register Sequences Section,
Fastlock: An Example Section, and Fastlock: Loop Filter
Topology Section ............................................................................ 19
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Added Operating with Wide Loop Filter Bandwidths
Section.............................................................................................. 20
Updated Outline Dimensions ....................................................... 21
7/07—Revision 0: Initial Version
Rev. D | Page 2 of 24
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