AD7949 View Datasheet(PDF) - Analog Devices
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AD7949 Datasheet PDF : 32 Pages
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AD7949
TIMING SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
Data Write/Read During Conversion
CNV Pulse Width
SCK Period
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV Low to SDO D15 MSB Valid
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.8 V
CNV High or Last SCK Falling Edge to SDO High Impedance
CNV Low to SCK Rising Edge
DIN Valid Setup Time from SCK Rising Edge
DIN Valid Hold Time from SCK Rising Edge
Symbol
tCONV
tACQ
tCYC
tDATA
tCNVH
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
Min
Typ
1.8
4.0
10
tDSDO + 2
11
11
4
tEN
tDIS
tCLSCK
10
tSDIN
5
tHDIN
5
1 See Figure 2 and Figure 3 for load conditions.
Data Sheet
Max
Unit
2.2
µs
µs
µs
1.0
µs
ns
ns
ns
ns
ns
18
ns
23
ns
28
ns
18
ns
22
ns
25
ns
32
ns
ns
ns
ns
Rev. F | Page 6 of 32
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