AD1884A View Datasheet(PDF) - Analog Devices
Part Name
Description
View to exact match
AD1884A Datasheet PDF : 20 Pages
| |||
AD1884A
Table 4. Pin Function Descriptions
Mnemonic
Pin No.
I/O
Description
DIGITAL INTERFACE
SDATA_OUT
5
BIT_CLK
6
SDATA_IN
8
SYNC
10
RESET
11
DIGITAL I/O and EAPD
GPIO_2
30
MIC_BIAS-E/GPIO_1
31
EAPD/GPIO_0
47
S/PDIF_OUT
48
JACK SENSE
SENSE_A/SRC_B
13
SENSE_B/SRC_A
34
ANALOG I/O
PCBEEP
12
PORT-E_L
14
PORT-E_R
15
PORT-F_L
16
PORT-F_R
17
CD_GND (PORT-F)
19
I
Link Serial Data Output. AD1884A input stream. Clocked on both edges of the
BIT_CLK.
I
Link Bit Clock. 24.000 MHz serial data clock.
I/O
Link Serial Data Input. AD1884A output stream clocked only on one edge of BIT_CLK.
I
Link Frame Sync.
I
Link Reset. AD1884A master hardware reset.
I/O
General-Purpose Input/Output Pin. Digital signal used to control or sense external
circuitry.
I/O
Microphone Bias for Port E/General-Purpose Input/Output. Capable of high-Z, 1.65 V,
and 2.86 V. Pin 31 shares functionality between MIC_BIAS-E (default) and GPIO_1.
These functions are mutually exclusive and the MIC_BIAS function takes priority over
the GPIO function.
I/O
EAPD/General-Purpose Input/Output Pin. Pin 47 shares functionality between
GPIO_0 and EAPD. These functions are mutually exclusive and the EAPD function
takes priority over the GPIO function. By default, the pin is in a high-Z state. External
resistors should be used to ensure the proper circuit state when this pin is in high-Z.
O
Supports S/PDIF Output.
I/O
Jack Sense A-D Input/Sense B Drive.
I/O
Jack Sense E-F Input/Sense A Drive.
LI
Monaural Input from System for Analog PCBeep.
LI, MIC, LO Auxiliary Input/Output Left Channel.
LI, MIC, LO Auxiliary Input/Output Right Channel.
LI, LO Auxiliary Input/Output Left Channel.
LI, LO Auxiliary Input/Output Right Channel.
I
CD Audio Analog Ground Reference. Must be connected to AGND via a 0.1 μF
capacitor if not in use as CD_GND. MUST always be ac-coupled.
PORT-B_L
21
PORT-B_R
22
PORT-C_L
23
PORT-C_R
24
MONO_OUT
32
PORT-D_L
35
PORT-D_R
36
PORT-A_L
39
PORT-A_R
41
FILTER/MIC_BIAS
VREF _FLT
27
MIC_BIAS-B
28
MIC_BIAS-C
29
MIC_BIAS_IN
33
5.0 V or 3.3 V
LI, MIC
LI, MIC
LI, MIC
LI, MIC
LO
HP, LO
HP, LO
HP, LO
HP, LO
O
O
O
I
Front Panel Stereo MIC/Line-In.
Front Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Voltage Reference Filter.
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
Both MIC bias pins are capable of:
High-Z, 0 V, 1.65 V, 3.7 V, and 3.9 V (with 5.0 V on Pin 33)
High-Z, 0 V, 1.65 V, 2.86 V, and 3.0 V (with 3.3 V on Pin 33).
Source Power for Microphone Bias Boost Circuitry.
Connect this pin to 5.0 V via a low-pass filter. When connected this way, the AD1884A
is capable of providing 3.9 V as a mic bias to all of the mic bias pins (except on Pin 31).
If 5 V is not available, connect this pin to 3.3 V (AVDD) via a low-pass filter.
The symbols used in this table are defined as: I = input, O = output, LI = line level input, LO = line level output, HP = output capable of driving
headphone load, MIC = input supports microphones with MIC bias and boost amplifier.
Rev. 0 | Page 10 of 20 | March 2008
Share Link: 