A43L2632V-6 View Datasheet(PDF) - AMIC Technology

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Description

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A43L2632V-6

1M X 32 Bit X 4 Banks Synchronous DRAM

AMIC Technology 

8. Burst Stop & Interrupted by Precharge

1) Normal Write (BL=4)

CLK

CMD

WR

PRE

DQM

DQ

D0 D1 D2 D3

tRDL Note 1

1) Read Interrupted by Precharge (BL=4)

CLK

CMD

RD

DQ(CL2)

PRE

Q0

Note 3

Q1 1

DQ(CL3)

Q0 Q1 2

A43L2632

2) Write Burst Stop (BL=8)

CLK

CMD

WR

STOP

DQM

DQ

D0 D1 D2 D3 D4 D5

tBDL Note 2

4) Read Burst Stop (BL=4)

CLK

CMD

RD

STOP

DQ(CL2)

Q0 Q1 1

DQ(CL3)

Q0 Q1 2

9. MRS

Mode Register Set

CLK

CMD

Note 1

PRE

tRP

MRS

ACT

2CLK

Note : 1. tRDL: 1CLK

2. tBDL: 1CLK; Last data in to burst stop delay.

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.

4. PRE: All banks precharge if necessary.

MRS can be issued only when all banks are in precharged state.

PRELIMINARY (January, 2005, Version 0.0)

20

AMIC Technology, Corp.

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