28F128 View Datasheet(PDF) - Intel
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28F128 Datasheet PDF : 58 Pages
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28F128J3A, 28F640J3A, 28F320J3A
Product Overview
The 0.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as
16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized
as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is
organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two
128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-
system. A 128-bit protection register has multiple uses, including unique flash device
identification.
The device’s optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second—
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments. This feature can
improve system program performance more than 20 times over non-Write Buffer writes.
Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block
erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block
Lock-Bit and Clear Block Lock-Bits commands).
The status register indicates when the WSM’s block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit
configuration. STS-high indicates that the WSM is ready for a new command, block erase is
Preliminary
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