VS1003 View Datasheet(PDF) - Unspecified

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VS1003

MP3/WMA AUDIO CODEC

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VS1003

7 SPI BUSES

7.3 Data Request Pin DREQ

The DREQ pin/signal is used to signal if VS1003’s FIFO is capable of receiving data. If DREQ

is high, VS1003 can take at least 32 bytes of SDI data or one SCI command. When these

criteria are not met, DREQ is turned low, and the sender should stop transferring new data.

Because of the 32-byte safety area, the sender may send up to 32 bytes of SDI data at a

time without checking the status of DREQ, making controlling VS1003 easier for low-speed

microcontrollers.

Note: DREQ may turn low or high at any time, even during a byte transmission. Thus, DREQ

should only be used to decide whether to send more bytes. It should not abort a transmission

that has already started.

Note: In VS10XX products up to VS1002, DREQ was only used for SDI. In VS1003 DREQ is

also used to tell the status of SCI.

There are cases when you still want to send SCI commands when DREQ is low. Because

DREQ is shared between SDI and SCI, you can not determine if a SCI command has been

executed if SDI is not ready to receive. In this case you need a long enough delay after every

SCI command to make certain none of them is missed. The SCI Registers table in section 8.6

gives the worst-case handling time for each SCI register write.

7.4 Serial Protocol for Serial Data Interface (SDI)

7.4.1 General

The serial data interface operates in slave mode so DCLK signal must be generated by an

external circuit.

Data (SDATA signal) can be clocked in at either the rising or falling edge of DCLK (Chapter 8.6).

VS1003 assumes its data input to be byte-sychronized. SDI bytes may be transmitted either

MSb or LSb first, depending of contents of SCI_MODE (Chapter 8.6.1).

The firmware is able to accept the maximum bitrate the SDI supports.

7.4.2 SDI in VS10xx Native Modes (New Mode, recommended)

In VS10xx native modes (SM_NEWMODE is 1), byte synchronization is achieved by XDCS.

The state of XDCS may not change while a data byte transfer is in progress. To always main-

tain data synchronization even if there may be glitches in the boards using VS1003, it is rec-

ommended to turn XDCS every now and then, for instance once after every flash data block or

a few kilobytes, just to keep sure the host and VS1003 are in sync.

If SM_SDISHARE is 1, the XDCS signal is internally generated by inverting the XCS input.

For new designs, using VS10xx native modes are recommended.

Version: 1.09, 2018-03-16

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