EPF011A View Datasheet(PDF) - Unspecified
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Description
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EPF011A Datasheet PDF : 124 Pages
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2.3 Pin Description
User Guide — EPF011ACD_UG V0.2
Unless otherwise stated, unused input pins must be tied to ground, and unused output pins left open.
Name
OP_MODE
RSTb
X_IN
X_OUT
P0[7:0]
P1[3:0]
P2[7:1]
P3[5:0]
P4[4,1:0]
P5[7:0]
P6[3:0]
P7[4,1:0]
P8[7, 3:0]
P9[0]
TIM[1:0]
SPI_CLK
SPI_DO
DP
DM
ADC[3:0]
VDDA
VSSA
VDD
VSS
In/Out
IN
IN/OUT
IN
OUT
IN/OUT
IN/OUT
IN/OUT
OD IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
IN/OUT
PWR
PWR
PWR
PWR
Table 2-1 Pin Description
Buffer Type
IXDXXP
BDUX8P
XTL24P
XTL24P
BRXX12P
BRUX8P
BRXX8P
BRXX8P
BRXX8P
BRXX24P
BRXX24P
BRXX8P
BRXX8P
BRXX8P
BRXX8P
BRXX8P
BRXX8P
USB
USB
ADC
-
-
-
-
Description
Chip operation mode.
0: Normal mode
1: ICP (In Circuit Flash Programming) mode
External Reset (active low) with on-chip pull-up. When this pin
is asserted low, the chip is totally reset. When the on-chip LVI
circuit is generating a chip reset, a low level will be output
from this pin.
24 Mhz crystal input
24 Mhz crystal output
GPIO port 0 with programmable Open Drain capability.
GPIO port 1 or Keyboard Interrupt inputs with internal 20KΩ
pull-up to VDD
GPIO port 2 with programmable Open Drain capability.
Open Drain I/O port 3. P3[5:0] shared with IIC.
GPIO port 4 or External Interrupt inputs
GPIO port 5 with programmable Open Drain capability
GPIO port 6 with 20 mA drive
Open Drain I/O port 7. P7[1:0] shared with Serial Port. P7[4]
share with CIR.
GPIO port 8 with programmable Open Drain capability. P8[7]
and P8[3:0] share with PWM
GPIO port 9 with programmable Open Drain capability.
Timer In/Out or GPIO
SPI Clock Out or GPIO
SPI Data In/Out or GPIO
USB D+ In/Out or GPO
USB D- In/Out or GPO
ADC Inputs or GPIO
Analogue VDD (3.3V)
Analogue Ground
Digital VDD (3.3V)
Digital Ground
Confidential Proprietary
15
NON-DISCLOSURE AGREEMENT REQUIRED
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