MT9M011 View Datasheet(PDF) - Micron Technology
Part Name
Description
View to exact match
MT9M011 Datasheet PDF : 41 Pages
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Preliminary‡
MT9M011 - 1/3-Inch Megapixel Image Sensor
Pixel Data Format
Tabl.e 3: Frame Time
Parameter
A
P
Q
Name
Active Data Time
Frame Start/End
Blanking
Equation (master clocks units)
Reg0x04 x PIXCLK_PERIOD
(For skip 2x mode: divide Reg0x04 by 2,
For skip 4x mode: divide Reg0x04 by 4)
6 x PIXCLK_PERIOD
Horizontal Blanking HBLANK_REG x PIXCLK_PERIOD
A+Q
RowTime
(Reg0x04 + HBLANK_REG) x PIXCLK_PERIOD
V
Vertical Blanking
VBLANK_REG x (A + Q) + (Q - 2 x P)
Nrows x (A + Q) Frame Valid Time
F
Total Frame Time
Reg0x03 x (A + Q) - (Q - 2 x P)
(For skip 2x mode: divide Reg0x03 by 2,
For skip 4x mode: divide Reg0x03 by 4)
(Reg0x03 + VBLANK_REG) x (A + Q)
1ADC_MODE:
Reg0xC8, bit 3 = 1: Reg0x20, bit 10
Reg0xC8, bit 3 = 0: Reg0x21, bit 10 (0 = 2 ADC mode, 1 = 1 ADC mode)
Default = 0
HBLANK_REG:
Reg0xC8, bit 0 = 1: Reg0x05
Reg0xC8, bit 0 = 0: Reg0x07
1ADC_MODE = 0: Minimum value is 202, 1ADC_MODE = 1: Minimum value is 114
Default = 396 (13.9 fps)
Note: For frame rate of 15 fps, set Reg0x05 to 272
VBLANK_REG:
Reg0xC8, bit 1 = 1: Reg0x06
Reg0xC8, bit 1 = 0: Reg0x08
Minimum value: sum of dark and extra rows enabled in Reg0x22 and Reg0x24
Default = 50
PIXCLK_PERIOD:
1ADC_MODE = 0: Reg0x0A, bit 3 - 0
1ADC_MODE = 1: (Reg0x0A, bit 3 - 0) x 2
A value of 0 in the register is not allowed.
Default = 1
Default Timing
at 25 MHZ
1,280 pixel clocks
= 1,280 master
= 51.2µs
6 pixel clocks
= 6 master
= 0.24µs
396 pixel clocks
= 396 master
= 15.84µs
1,676 pixel clocks
= 1,676 master
= 67.04µs
84,184 pixel clocks
= 84,184 master
= 3.37ms
1,715,840 pixel clocks
= 1,715,840 master
= 68.63ms
1,800,024 pixel clocks
= 1,800,024 master
= 72.0ms
PDF: 09005aef81051c04/Source: 09005aef8102abe8
MT9M011_2.fm - Rev. D 1/05 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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