M5M417400CTP-7 View Datasheet(PDF) - MITSUBISHI ELECTRIC
Part Name
Description
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M5M417400CTP-7 Datasheet PDF : 22 Pages
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MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
Write Cycle (Early Write and Delayed Write)
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
Max
Min
Max
Min
Max
tWC
Write cycle time
90
110
130
ns
tRAS
RAS low pulse width
50
10000
60
10000
70
10000
ns
tCAS
CAS low pulse width
13
10000
15
10000
20
10000
ns
tCSH
CAS hold time after RAS low
50
60
70
ns
tRSH
RAS hold time after CAS low
13
15
20
ns
tWCS
Write setup time before CAS low
(Note 22)
0
0
0
ns
tWCH
Write hold time after CAS low
8
10
10
ns
tCWL
CAS hold time after W low
13
15
20
ns
tRWL
RAS hold time after W low
13
15
20
ns
tWP
Write pulse width
8
10
10
ns
tDS
Data setup time before CAS low or W low
0
0
0
ns
tDH
Data hold time after CAS low or W low
8
10
15
ns
tOEH
OE hold time after W low
13
15
20
ns
Read-Write and Read-Modify-Write Cycles
Limits
Symbol
Parameter
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Unit
Min
Max
Min
Max
Min
Max
tRWC
Read write/read modify write cycle time
(Note 21)
131
155
180
ns
tRAS
tCAS
tCSH
tRSH
tRCS
RAS low pulse width
CAS low pulse width
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
91
10000
105
10000
120
10000
ns
54
10000
60
10000
70
10000
ns
91
105
120
ns
54
60
70
ns
0
0
0
ns
tCWD
Delay time, CAS low to W low
(Note 22)
36
40
45
ns
tRWD
Delay time, RAS low to W low
(Note 22)
73
85
95
ns
tAWD
Delay time, address to W low
(Note 22)
48
55
60
ns
tCWL
CAS hold time after W low
13
15
20
ns
tRWL
RAS hold time after W low
13
15
20
ns
tWP
Write pulse width
8
10
10
ns
tDS
Data setup time before W low
0
0
0
ns
tDH
tOEH
Data hold time after W low
OE hold time after W low
8
10
15
ns
13
15
15
ns
Note 21:
Note 22:
tRWC is specified as tRWC(min) = tRAC(max) + tODD(min) + tRWL(min) + tRP(min) + 5tT.
tWCS, tCWD, tRWD and tAWD and, tCPWD are specified as reference points only. If tWCS ≥ tWCS(min) the cycle is an early write cycle and the DQ pins will remain high impedance
throughout the entire cycle. If tCWD ≥ tCWD(min), tRWD ≥ tRWD(min), tAWD ≥ tAWD(min) and tCPWD ≥ tCPWD(min) (for fast page mode cycle only), the cycle is a read-modify-write
cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access time and until CAS or OE goes
back to VIH) is indeterminate.
6
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