JBT6K49-AS View Datasheet(PDF) - Toshiba

Part Name

Description

View to exact match

JBT6K49-AS

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

Toshiba 

PAD Specifications

Characteristics

Chip Size

(1)

(2)

Chip End Coordinates

(3)

(4)

Bump Pitch

Bump Height

Size

Unit

4600 ´ 3050

mm

-2300, 1525

-2300, -1525

mm

2300, -1525

2300, 1525

140

mm

15

mm

JBT6K49-AS

Characteristics

Number of Pins

TEG pin

9

FUSE pin

22

Note 1: The TEG1 to TEG9 pins and the FUSE** pins are reserved for testing by Toshiba. They are not intended to

for use in the operation of the JBT6K49-AS. They must always be left open during normal operation.

Alignment Mark Specifications

X and Y

coordinates

AI

Non-designed area

90 mm

100 mm

90 mm

100 mm

90 mm

90 mm

3

2002-03-12

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