IDT72510L25J View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

COMMERCIAL TEMPERATURE RANGE

Write

DSA

1

2

n+1

RB

(or R/WB=1, DS B)

A→B

Empty Flag

A→B

Almost-Empty Flag

tWEF

tWAEF

Read

2n+1 2n+2

1

2

3

4

tREF

tRAEF

Figure 22. Empty and Almost-Empty Flag Timing for AÆB FIFO. (n = Programmed Offset)

2669 drw 24

NOTES:

1. AÆB FIFO is initially empty.

2. Assume the flag pins are programmed active LOW.

3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads

must be doubled.

4. R/WA = 1

DSA

RB

(or R/WB=1, DSB)

B→A

Almost- Full

Flag

B→A Full

Flag

Write

1

2

m+1

tWAFF

tWFF

Read

2m+ 2m+

1

2

3

4

1

2

tRAFF

tRFF

2669 drw 25

Figure 23. Full and Almost-Full Flag Timing for AÆB FIFO. (m = Programmed Offset)

NOTES:

1. AÆB FIFO initially contains D–(M+1) data words. D = 512 for IDT 72510;

D = 1024 for IDT72520.

2. Assume the flag pins are programmed active LOW.

3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads

must be doubled.

4. R/WA = 0

5.31

31

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