IDT72510L25J View Datasheet(PDF) - Integrated Device Technology

Part Name

Description

MFG CO.

IDT72510L25J

BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT

Integrated Device Technology 

IDT72510, IDT72520

BUS MATCHING BIDIRECTIONAL FIFO

COMMERCIAL TEMPERATURE RANGE

DSA

WB

(or R/WB=0,

DSB)

B→A

Empty Flag

B→A Almost-

Empty Flag

Write

1

2

3

4

tWEF

2n+1 2n+2

tWAEF

Read

1

2

tRAEF

Figure 20. Empty and Almost-Empty Flag Timing for BÆA FIFO. (n = Programmed Offset)

NOTES:

1. BÆA FIFO is initially empty.

2. Assume the flag pins are programmed active LOW.

3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads

must be doubled.

4. R/WA = 1

n+1

tREF

2669 drw 22

DSA

WB

(or R/WB=0,

DSB)

Write

1

2

B→A Almost-

Full Flag

B→A

Full Flag

3

4

tWAFF

2m+1 2m+2

tWFF

Read

1

2

m+1

tRAFF

tRFF

2669 drw 23

Figure 21. Full and Almost-Full Flag Timing for BÆA FIFO. (m = Programmed Offset)

NOTES:

1. BÆA FIFO initially contains D–(M+1) data words. D = 512 for IDT 72510;

D = 1024 for IDT72520.

2. Assume the flag pins are programmed active LOW.

3. For stand-alone mode only; in a 36- to 9-bit configuration, Port B reads

must be doubled.

4. R/WA = 1

5.31

30

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