IDT72103 View Datasheet(PDF) - Integrated Device Technology
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IDT72103 Datasheet PDF : 30 Pages
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IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
OUTPUTS:
Data Outputs (Q0–Q8)
Data outputs for 9-bit wide data. These output lines are in
a high-impedance condition whenever R is in a high state. The
serial output mode is selected by grounding the SO/PO pin.
The Q0-Q8 lines are control pins used to program the serial
word width.
Serial Output (SO)
Serial data is output on the SO pin. In both depth and serial
width expansion modes the serial output signals of the
different FlFOs in the expansion array are connected to-
gether. Following reset, SO is tristated until the first rising
edge of the Serial Out Clock (SOCP) signal. Data is clocked
out least significant bit first. In the serial width expansion
mode, SO is tristated again after the ninth bit is output.
Full Flag (FF)
FF is asserted LOW when the FIFO is full. When the FIFO
is full, the internal write pointer will not be incremented by any
additional write pulses.
Full Flag — Serial In Mode
When the FIFO is loaded serially, the Serial In Clock (SICP)
asserts the FF. On the second rising edge of the SICP for the
last word in the FIFO, the FF will assert LOW, and it will remain
asserted until the next read operation. Note that when the FF
is asserted, the last SICP for that word will have to be stretched
as shown in Figure 23.
Full Flag — Parallel–ln Mode
When the FIFO is in the Parallel-ln mode, the falling edge
of W asserts the FF (LOW). The FF is then de-asserted (HIGH)
by subsequent read operations - either serial or parallel.
Full–Minus — One Flag (FF–1)
The FF–1 flag is asserted low when the FIFO is one word
away from being full. It will remain asserted when the FIFO is
full.
Expansion Out/Half–Full Flag (XO/HF)
In the single-device mode, the XO/HF pin operates as a HF
pin when the Xl pin is grounded. After half of the memory is
filled, the HF will be set to LOW at the falling edge of the next
write operation. It will remain set until the difference between
the write pointer and read pointer is less than or equal to one-
half of the FIFO total memory. The HF is then reset by the
rising edge of the read operation.
In the multiple-device mode, the XI pin is connected to the
XO pin of the previous device. The XO pin signals a pulse to
the next device when the previous device reaches the best
location of memory in the daisy chain configuration.
Almost–Empty or Almost–Full Flag (AEF)
The AEF asserts LOW if there are 0-255 or 1,793-2,048
bytes in the IDT72103, 2,048 x 9 FIFO. The AEF asserts LOW
if there are 0-511 or 3,585-4,096 bytes in the IDT72104,
4,096 x 9 FIFO.
Empty–Plus–One Flag (EF+1)
In the parallel-output mode, the EF+1 flag is asserted LOW
when there is one word or less in the FIFO. It will remain LOW
when the FIFO is empty.
In the serial-output mode, the EF+1 flag operates as an
EF+2 flag. It goes LOW when the second to the last word is
read from the RAM array and is ready to be shifted out.
Empty Flag (EF) — Parallel–Out Mode
When the FIFO is in the parallel out mode and there is only
one word in the FIFO, the falling edge of the R line will cause
the EF line to be asserted LOW. This is shown in Figure 6. The
EF is then de-asserted HIGH by either the rising edge of W or
the rising edge of SICP, as shown in Figure 6.
Empty Flag — Serial–Out Mode
The use of the EF is important for proper serial-out opera-
tion when the FIFO is almost empty. The EF flag is asserted
LOW after the first bit of the last word is shifted out. This is
shown in Figure 22.
TABLE 1 — STATUS FLAGS
Number of
Words in FIFO
IDT72103 IDT72104
(1)
FF FF-1 AEF HF EF+1 EF
0
0
HH LH L L
1
1
HH LH LH
2-255
2-511
HH LHHH
' 256-1,024 512-2,048 H H H H H H
1,025-1,792 2,049-3,584 H H H L H H
1,793-2,046 3,585-4,094 H H L L H H
2,047
4,095
H L L LHH
2,048
4,096
L L L LHH
NOTE:
1. EF+1 acts as EF+2 in the serial out mode.
2753 tbl 10
8
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