HB7121B View Datasheet(PDF) - Hynix Semiconductor
Part Name
Description
View to exact match
HB7121B Datasheet PDF : 29 Pages
| |||
Electronics Industries Co., Ltd.
System IC Division
PRELIMINARY
(9) VSYNC Blanking Time Register
HB7121B
CMOS IMAGE SENSOR
With 8-bit ADC
(Higher byte : Address 22h, default : 00h, R/W)
(Lower byte : Address 23h, default : 03h, R/W)
The VSYNC blank, and time defines VSYNC active duration in pixel unit .
<Note>
HSYNC blanking, VSYNC blank are used to fit the CMOS sensor display timing to external timing
requirements.
(10) Integration time Register
(High byte : Address 25h, default : 00h, R/W)
(Middle byte : Address 26h, default : 01h, R/W)
(Low byte : Address 27h, default : f4h, R/W)
Each pixel has a photo diode in which the incoming photons are converted to electrons. Integration
time mean exposure time so these registers defines exposure time.
According to settings int_sel of Mode B register, the integration time is controlled with line or pixel
unit. Small value means short exposure time and large value means long exposure time for bright
condition.
The value should be large for dark condition. Default value setting 500 lines, this value is useful for
normal office condition. If you stay in outdoor condition, this value should be decreased. But under
dark condition, this value should be increased to get a good image quality. Increasing value may
decrease frame rate. Finally, integration time is very important for frame rate and image quality.
For line mode exposure, register 26h and 27h are used. For pixel mode exposure, all three register
25h ~ 27h are used. To control exposure time precisely, the pixel mode should be used. This register
may be used for Auto Exposure control.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. NO patent licenses are implied.
DA21991011R_1.0
- 17 -
1999 Hyundai System IC Division
Share Link: 