CY7C4241V-25AC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C4241V-25AC Datasheet PDF : 18 Pages
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CY7C4421V/4201V/4211V/4221V
CY7C4231V/4241V/4251V
Switching Waveforms (continued)
Programmable Almost Full Flag Timing
WCLK
tCLKH
WEN1
tCLKL
tENS tENH
Note 21
WEN2
(if applicable)
PAF
RCLK
tENS tENH
FULL − (M+1) WORDS
IN FIFO
[22]
tPAF
FULL − M WORDS
IN FIFO [23]
tSKEW2[24]
tPAF
REN1,
REN2
Write Programmable Registers
tENS
tENS tENH
WCLK
tCLKH
WEN2/LD
WEN1
D0 –D8
tCLK
tCLKL
tENS
tENS
tENH
tDS
tDH
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Notes:
21. If a write is performed on this rising edge of the write clock, there will be Full – (m–1) words of the FIFO when PAF goes LOW.
22. PAF offset = m.
23. 64–m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512–m words for CY7C4211V, 1024–m words for CY7C4221V, 2048–m words for
CY7C4231V, 4096–m words for CY7C4241V, 8192–m words for CY7C4251V.
24. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06010 Rev. *B
Page 14 of 18
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