CY7C4201V(2003) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

View to exact match

CY7C4201V
(Rev.:2003)

Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421V/4201V/4211V/4221V

CY7C4231V/4241V/4251V

Switching Waveforms (continued)

Reset Timing[13]

tRS

RS

REN1,

REN2

tRSS

tRSS

tRSR

tRSR

WEN1

WEN2/LD [15]

tRSS

tRSR

EF,PAE

tRSF

tRSF

FF,PAF,

Q0 − Q8

tRSF

OE=1 [14]

Notes:

OE=0

13. The clocks (RCLK, WCLK) can be free-running during reset.

14. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.

15. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the

programmable flag offset registers.

Document #: 38-06010 Rev. *A

Page 10 of 17

Share Link: