CXB1451Q View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
View to exact match
CXB1451Q Datasheet PDF : 13 Pages
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CXB1451Q
Pin List
Power/Ground
Pin Name
Pin Number
Descriptions
VCCT
VEET
VCCG
VEEG
VCCE
VEEE
VCCA
VEEA
VEES
10, 20, 30, 40, 48, 70, 80
1, 11, 21, 31, 41, 71
25, 32, 69, 76
26, 33, 68, 75
54
51
56
57
58
TTL power surpply , should be connected to 3.3V ± 5%
TTL ground, connected to 0V
Logical core power surpply, connected to 3.3V ± 5%
Logical core ground, connected to 0V
Serial driver power surpply, connected to 3.3V ± 5%
Serial driver ground, connected to 0V
Analog power surpply, connected to 3.3V ± 5%
Analog ground, connected to 0V
Analog substrate, connected to 0V
Digital Signals
Pin Name
Pin Number
SFTCLK
72
RED1 (5 to 0) 14, 15, 16, 17, 18, 19
GRN1 (5 to 0) 6, 7, 8, 9, 12, 13
BLU1 (5 to 0) 78, 79, 2, 3, 4, 5
RED0 (5 to 0) 42, 43, 44, 45, 46, 47
GRN0 (5 to 0) 34, 35, 36, 37, 38, 39
BLU0 (5 to 0) 22, 23, 24, 27, 28, 29
HSYNC
73
VSYNC
74
CNTL (3 to 0) 65, 66, 67, 77
PANEL (1, 0) 62, 63
CKMODE
64
IDLE
49
SDATAP/N 52, 53
REFREQ
50
Type
Descriptions
TTL in Shift clock, for the data fetch at rising or falling edge
TTL in
Pixel data input in 1 pixcel/sftclk mode
2nd pixel data input in 2 pixel/sftclk mode
TTL in
Ignored in 1 pixcel/sftclk mode
1st pixel data input in 2 pixel/sftclk mode
TTL in Hsync data
TTL in Vsync data
TTL in Control data
TTL in Panel mode select switch
TTL in Clock mode select switch
TTL in Idle mode select switch
Tx
Serial Output & Refclk request input
TTL out Refclk request detect flag
Special
Pin Name Pin Number
Descriptions
TESTSB/DT 55, 61
SFTCLK polarity / TEST function control
LPFA/B
59, 60
External loop filter
–2–
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