Preliminary Spec.
Some of contents are subject to change without notice.
MITSUBISHI LSIs
MH4V36AM-6,-7
FAST PAGE MODE 150994944-BIT ( 4194304-WORD BY 36-BIT ) DYNAMIC RAM
Timing Diagrams (Note 28)
Read Cycle
tRC
tRAS
VIH
RAS
VIL
VIH
CAS
VIL
VIH
A0 ~ A11
VIL
tCRP
tRCD
tCSH
tRSH
tCAS
tRAD
tASR tRAH
ROW
ADDRESS
tASC
tRAL
tCAH
COLUMN
ADDRESS
VIH
W
VIL
tRCS
tDZC
tRP
tRPC tCRP
tCPN
tRCH
tASR
tRRH
ROW
ADDRESS
tCDD
DQ
VIH
(INPUTS) VIL
DQ
VOH
(OUTPUTS) VOL
VIH
OE
VIL
tCAC
tAA
tCLZ
Hi-Z
tRAC
tDZO
Hi-Z
tOFF
DATA VALID
tOEZ
tOEA
tOCH
tODD
Hi-Z
tORH
MIT-DS-0071-0.1
Note 28
Indicates the don't care input.
VIH(min)≤VIN≤VIH(max) or VIL(min)≤VIN≤VIL(max)
Indicates the invalid output.
Indicates the skew of the four inputs.
MITSUBISHI
ELECTRIC
( 7 / 18 )
Sep./19 /1996