VV6301 View Datasheet(PDF) - Vision
Part Name
Description
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VV6301 Datasheet PDF : 51 Pages
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VV5301 & VV6301
Operating Modes
3.3 System Clock Generation
VV5301/VV6301 generates a system clock when a quartz crystal or ceramic resonator circuit is connected to the CLKI and CLKO
pins. The device can also be driven directly from an external clock source driving CLKI.
CLK
VV5301/VV6301
CLOCK
DIVISION
CLK
VV5301/VV6301
CLOCK
DIVISION
CKIN
C1=C2=47pF
31
R1=1MΩ
R2=510Ω
X1= 14.318MHz (up to 30fps)
17.73MHz (up to 25fps)
C1
CKOUT
R1
32
R2
C2
X1
CKIN
31
Clock
Source
CMOS Driver
Figure 4 : Camera Clock Source
CKOUT
32
For greater flexibility the input frequency can be divided by 1, 2, 4 or 8 to select the pixel clock frequency. Two bits in the clock
division register in the serial interface select the input clock frequency divisor. The table below gives the different frame rates that
can be selected, when CLKI = 14.318MHz, for up to 30frames per second, for each divisor.
CLKI (MHz)
14.318
14.318
14.318
14.318
Divisor
Pixel Period (us)
Frame Rate
1
1.1175
29.99
2
2.235
15.01
4
4.47
7.5
8
8.94
3.75
Table 3 : Clock Division (60Hz Video Mode)
Comments
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3.4 Calculating Sensor Framerate
The VV5301/VV6301 frame rate depends upon:
• the frequency of the system clock (CLKI)
• the ADC conversion accuracy (8-bit)
• the internal clock divisor selected (1, 2, 4, or 8)
• the output format is a constant 2
User can set their own values for CLKI and also the clock divisor setting. The frame rate is determined as follows
An example is given with a clock input of 14.318MHz, 160 x120 (164 x 124) image format, 8-bit ADC conversion rate and a clock
divisor of 2.
1.
Determine clock input (CLKI) frequency - 14.318MHz
2.
Pixel period = (divisor x conversion factor x output format factor) / CLKI
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