CAM35C44 View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

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CAM35C44

Infrared Communications Controller Chip CameraFR

SMSC -> Microchip 

REGISTER ADDRESS MAP

Register addressing in the CAM35C44 is fixed

and requires a 32-byte memory block. Typically,

register addressing is accomplished with a 5 bit

address bus and a 1 bit chip select.

TABLE 9 describes the mapping for the four

register banks in the CAM35C44 address

space, CONFIGURATION, GPIO, ACE and

SCE, that are required for device configuration

and run-time control.

The external address pins that are responsible

for register addressing will depend on the Host

Interface Select bits (see section MULTIHOST

CPU INTERFACE on page 13).

8-BYTE

ADDRESS

BANK

0

1

2

3

TABLE 9 - CAM35C44 REGISTER MAP

BANK

SELECT

BITS

ADDRESS RANGE

SA[4:0] 1

REGISTER BANK DECODING

SA4

SA3

0

0

0x00 - 0x07

CONFIGURATION

0

1

0x08 - 0x0F

GPIO

1

0

0x10 - 0x17

ACE

1

1

0x18 - 0x1F

SCE

Note1 Address Enable (AEN) must be low to access the CAM35C44 registers regardless of the state

of the Host Interface Select bits.

Non-Multiplexed (ISA) Addressing

As shown in TABLE 9 five address bits SA[4:0]

and a chip select nCS are required to access the

CAM35C44 run-time and configuration registers.

address, while nCS decodes the 32-byte

address block. Note: address block decoding

must be done externally.

In ISA mode, five bits of the ISA System Address

bus SA[4:0] determine the register

The Block Select bits BS[2:0] and two of the

general purpose I/Os GPIO[4:3] are unavailable

in ISA mode.

16

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