GL811USB View Datasheet(PDF) - Genesys Logic

Part Name

Description

View to exact match

GL811USB

USB 2.0 to ATA / ATAPI Bridge Controller

Genesys Logic 

GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller

3.2.8 FIFOs

Control FIFO is used as Control Read / Write FIFO. TXFIFO0 / TXFIFO1 are two

sets of 512-byte ping-pong FIFO for Bulk Read endpoint. It buffers data from IDE

engine, and re-direct to USB SIE logic. RXFIFO0 / RXFIFO1 are two sets of

512-byte ping-pong FIFO for Bulk Write endpoint. It buffers data from USB SIE

logic, and re-direct to IDE engine.

3.2.9 Control Registers

Control Register configures GL811USB to proper operation. For example, CPU

can set register to generate wakeup event, enter suspend, transmits proper USB

packet to host.

©2000-2002 Genesys Logic Inc.—All rights reserved.

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