GL711FW View Datasheet(PDF) - Genesys Logic

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GL711FW

ATA/ATAPI to 1394 Native Bridge Two in One Solution

Genesys Logic 

GL711FW

Management ORB agent pointer (2 quadlets), Command ORB agent pointer (2 quadlets),

Management ORB (8 quadlets), Command ORB (8 quadlets), Page Table pointer (2

quadlets), general Rx data payload (8 quadlets), and general data moved from or to initiator

(1K quadlets).

7. SBP-2 Registers: the registers for received data payload of SBP-2 associated packet

including Management ORB agent pointer (2 quadlets), Command ORB agent pointer

(2 quadlets), Management ORB (8 quadlets), Command ORB (8 quadlets) and Page Table

pointer (2 quadlets).

8. Tx/Rx Data FIFO: 4 Kbytes of ping-pong buffer for data moved between the initiator and

target.

9. IDE Ultra DMA Engine: control the interface to IDE device and automatically access

data with IDE DMA or IDE UDMA mode.

10. I/O Control Registers: a register space to store information about status, packet and chip,

accessible by system ASIC and µP.

11. IDE Interface: an interface for accessing IDE device internal registers.

12. 8051 Micro-controller: an embedded processor for SBP2-2 to ATA/ATAPI command

transaction.

Revision: 1.3

-6-

09/12/2001

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