SST89V516RD2-33-C-TQJE View Datasheet(PDF) - Microchip Technology
Part Name
Description
View to exact match
SST89V516RD2-33-C-TQJE Datasheet PDF : 94 Pages
| |||
FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
SPI Control Register (SPCR)
Location
D5H
7
SPIE
Data Sheet
6
SPE
5
DORD
4
MSTR
3
CPOL
2
CPHA
1
SPR1
0
Reset Value
SPR0
00H
Symbol Function
SPIE If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE SPI enable bit.
0: Disables SPI.
1: Enables SPI and connects SS#, MOSI, MISO, and SCK to pins P1.4, P1.5, P1.6, P1.7.
DORD
Data Transmission Order.
0: MSB first in data transmission.
1: LSB first in data transmission.
MSTR
Master/Slave select.
0: Selects Slave mode.
1: Selects Master mode.
CPOL
Clock Polarity
0: SCK is low when idle (Active High).
1: SCK is high when idle (Active Low).
CPHA
Clock Phase control bit. The CPHA bit with the CPOL bit control the clock and data
relationship between master and slave. See Figures 21 and 22.
0: Shift triggered on the leading edge of the clock.
1: Shift triggered on the trailing edge of the clock.
SPR1, SPR0SPI Clock Rate Select bits. These two bits control the SCK rate of the device configured
as master. SPR1 and SPR0 have no effect on the slave. The relationship between SCK and
the oscillator frequency, fOSC, is as follows:
SPR1
0
0
1
1
SPR0
0
1
0
1
SCK = fOSC divided by
4
16
64
128
SPI Status Register (SPSR)
Location
7
6
5
4
3
2
1
AAH
SPIF WCOL
-
-
-
-
-
Symbol Function
SPIF
SPI Interrupt Flag.
Upon completion of data transfer, this bit is set to 1.
If SPIE =1 and ES =1, an interrupt is then generated.
This bit is cleared by software.
WCOL Write Collision Flag.
Set if the SPI data register is written to during data transfer.
This bit is cleared by software.
0
Reset Value
-
00xxxxxxb
©2013 Silicon Storage Technology, Inc.
30
DS25093B
02/13
Share Link: 