IDT72264L15PF View Datasheet(PDF) - Integrated Device Technology
Part Name
Description
View to exact match
IDT72264L15PF
Integrated Device Technology
IDT72264L15PF Datasheet PDF : 31 Pages
| |||
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO™
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
In the serial method, SEN together with LD are used to load
the offset registers via the Serial Input (SI). In the parallel
method, WEN together with LD can be used to load the offset
registers via Dn. REN together with LD can be used to read the
offsets in parallel from Qn regardless of whether serial or
parallel offset loading is selected.
During Master Reset (MRS), the read and write pointers are
set to the first location of the FIFO. The FWFT line selects IDT
Standard Mode or FWFT Mode. The LD pin selects one of two
partial flag default settings (127 or 1023) and, also, serial or
parallel programming. The flags are updated accordingly.
The Partial Reset (PRS) also sets the read and write
pointers to the first location of the memory. However, the
mode setting, programming method, and partial flag offsets
are not altered. The flags are updated accordingly. PRS is
useful for resetting a device in mid-operation, when repro-
gramming offset registers may not be convenient.
The Retransmit function allows the read pointer to be reset
to the first location in the RAM array. It is synchronized to
RCLK when RT is LOW. This feature is convenient for
sending the same data more than once.
If, at any time, the FIFO is not actively performing a function,
the chip will automatically power down. This occurs if neither
a read nor a write occurs within 10 cycles of the faster clock,
RCLK or WCLK. During the Power Down state, supply current
consumption (ICC2) is at a minimum. Initiating any operation
(by activating control inputs) will immediately take the device
out of the Power Down state.
The IDT72264/72274 are depth expandable. The addition
of external components is unnecessary. The IR and OR
functions, together with REN and WEN, are used to extend the
total FIFO memory capacity.
The FS line ensures optimal data flow through the FIFO. It
is tied to GND if the RCLK frequency is higher than the WCLK
frequency or to Vcc if the RCLK frequency is lower than the
WCLK frequency
The IDT72264/72274 is fabricated using IDT’s high speed
submicron CMOS technology.
PIN CONFIGURATIONS (CONT.)
11
DNC Q5 VCC Q2 Q1 GND D1 D3 D5
10 Q6 GND Q4 Q3 GND Q0 D0 D2 D4 D6 D7
09 Q8 Q7
D9 D8
08 Q10 Q9
D11 D10
07 Q11 GND
D13 D12
06 Q13 Q12
D15 D14
05 Q14 VCC
04 GND Q15
Pin 1 Designator
D17 D16
VCC MAC
03 Q17 Q16
SEN FS
02 DNC OE REN GND PAE HF
FF/
IR
DNC
LD
WCLK WEN
01
RT
RCLK
EF/
OR
VCC
PAF
GND
FWFT/
SI
MRS
PRS
A B CDE F GHJ K L
3218 drw 03
PGA (G68-1, order code: G)
TOP VIEW
NOTES:
1. When the data path is selected to be 9 bits wide (MAC is HIGH), D9 - D17 may be tied to ground or left open, Q9 - Q17 must be left open.
2. DNC = Do not connect
3
Share Link: