CS51313GDR16 View Datasheet(PDF) - Cherry semiconductor

Part Name

Description

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CS51313GDR16

Synchronous CPU Buck Controller Capable of Implementing Multiple Linear Regulators

Cherry semiconductor 

Absolute Maximum Ratings

Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Lead Temperature Soldering

Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak

Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65° to 150°C

ESD Susceptibility (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV

Pin Symbol

VREF

VCC

Pin Name

Bandgap Reference Voltage

IC Power Input

COMP

VFB, VOUT, VID0-4

COFF

GATE(H), GATE(L)

Compensation Pin

Voltage Feedback Input, Output

Voltage Sense Pin, Voltage

ID DAC Inputs

Off-Time Pin

High-Side, Low Side FET Drivers

PWRGD

OVP

Gnd

Power-Good Output

Overvoltage Protection

Ground

VMAX

6V

16V

6V

6V

6V

16V

6V

15V

0V

VMIN

-0.3V

-0.3V

-0.3V

-0.3V

ISOURCE

1mA

N/A

1mA

1mA

ISINK

1mA

1.5A Peak

200mA DC

5mA

1mA

-0.3V

-0.3V

-0.3V

-0.3V

0V

1mA

1.5APeak

200mA DC

1mA

30mA

1.5A Peak

200mA DC

50mA

1.5A Peak

200mA DC

30mA

1mA

N/A

PACKAGE PIN #

1,2,3,4,6

9

10

11

12

14

16

15

8

7

5

13

Package Pin Description

PIN SYMBOL

VIDO – VID4

VCC

GATE(H)

Gnd

GATE(L)

PWRGD

COMP

COFF

VOUT

VFB

VREF

OVP

FUNCTION

Voltage ID DAC inputs. These pins are internally pulled up to

5.65V if left open. VID4 selects the DAC range. When VID4 is

high (logic one), the Error Amp reference range is 2.125V to

3.525V with 100mV increments. When VID4 is low (logic zero),

the Error amp reference voltage is 1.325V to 2.075V with 50mV

increments.

Input power supply pin for the internal circuitry.

Decouple with filter capacitor to Gnd.

High side switch FET driver pin

Ground pin.

Low side synchronous FET driver pin.

Power-Good Output. Open collector output drives low when

VFB is out of regulation.

Error amp output. PWM comparator inverting input.

A capacitor to Gnd provides error amp compensation.

Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets

the off time for the regulator

Current limit comparator inverting input.

Error amp inverting input, PWM comparator non-inverting

input, current limit comparator non-inverting input, PWRGD

and OVP comparator input.

Bandgap Reference Voltage. It can be used to generate other

regulated output voltages.

Overvoltage protection pin. Goes high when overvoltage

condition is detected on VFB.

2

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