PDI1394L41 View Datasheet(PDF) - Philips Electronics
Part Name
Description
View to exact match
PDI1394L41 Datasheet PDF : 81 Pages
| |||
Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
16.0 TIMING DIAGRAMS
16.1 AV Interface Operation
AVCLK
AV D[7:0]
MESSAGE
AVSYNC
INVALID DATA
MESSAGE
INVALID DATA
AVVALID
AVERR[0]
AVERR[1]
ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR
ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR
Figure 35. AV Parallel Interface Operation Diagram
16.2 AV Interface Critical Timings
AVCLK
ÉÉÉ AV D [7:0], AVVALID,
ÉÉÉ AVSYNC, AVENDPCK
SY, FSYNC, READY
AV D [7:0], AVERR[1:0],
AVSYNC, AVVALID
ÉÉÉÉÉÉ VALID
tWHIGH
tSU
tIH
tOD
tPERIOD
tWLOW
VALID
Figure 36. AV Interface Timing Diagram
MESSAGE
SV00240
SV00688
AVxFSYNC
tPWFS
Figure 37. AVxFSYNC Timing Diagram
SV00890
2000 Apr 15
72
Share Link: 