M37640E8 View Datasheet(PDF) - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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7600 Series
M37640E8-XXXF Preliminary Specification
Mitsubishi Microcomputers
MSB
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
fPIN
320 kHz
2 MHz
4 MHz
6 MHz
12 MHz
24 MHz
FSM1
Dec(n)
Hex(n)
74
4A
11
0B
5
05
3
03
1
01
0
00
fVCO/2(n+1) = fPIN
Bit 2
Bit 1
fVCO
48.00 MHz
48.00 MHz
48.00 MHz
48.00 MHz
48.00 MHz
48.00 MHz
Bit 0
LSB Address: 006D16
0 Access: R/W
Reset: FF16
Figure 2-10. Frequency Synthesizer Multiply Control register FSM1
MSB
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
fVCO
48.00 MHz
48.00 MHz
FSD
Dec(m)
Hex(m)
00
00
127
7F
fVCO/2(m+1) = fSYN
fSYN
24.00 MHz
187.50 KHz
Figure 2-11. Frequency Synthesizer Divide Register
LSB
0
Address: 006F16
Access: R/W
Reset: FF16
The relationship between fPIN, fVCO, and fSYN is as follows:
• fVCO = fPIN x 2(n+1) where n is the decimal equivalent of the value loaded in FSM2, FSM1.
Note: n must be chosen such that fVCO equals 48 MHz.
• fSYN = fVCO / 2(m+1) where m is the decimal equivalent of the value loaded in FSD
Note: Setting m = 255 disables the divider and disables fSYN.
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled
(FSC0 = “0”), fVCO is held at either a high or low state. When the frequency synthesizer control bit is
active (FSC0 = “1”), a lock status (LS = “1”) indicates that fSYN and fVCO are the correct frequency.
The LS and FSCO control bits in the FSC Control register are shown in Figure 2-12.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the
frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that
none of the registers be modified once the frequency synthesizer is enabled as it will cause the output
to be temporarily (2-5ms) unstable.
2-12
7/9/98
Oscillator Circuit
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