M38504M6-FP View Datasheet(PDF) - MITSUBISHI ELECTRIC

Part Name

Description

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M38504M6-FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

MITSUBISHI ELECTRIC  

MITSUBISHI MICROCOMPUTERS

3850 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

b7

b0

MISRG

(MISRG : address 003816)

Oscillation stabilizing time set after STP instruction

released bit

0: Automatically set “0116” to Timer 1,

“FF16” to Prescaler 12

1: Automatically set nothing

Middle-speed mode automatic switch set bit

0: Not set automatically

1: Automatic switching enable

Middle-speed mode automatic switch wait time set bit

0: 4.5 to 5.5 machine cycles

1: 6.5 to 7.5 machine cycles

Middle-speed mode automatic switch start bit

(Depending on program)

0: Invalid

1: Automatic switch start

Not used (return “0” when read)

Fig. 34 Structure of MISRG

Middle-speed mode automatic switch set bit

By setting the middle-speed mode automatic switch set bit to “1”

while operating in the low-speed mode, XIN oscillation automati-

cally starts and the mode is automatically switched to the

middle-speed mode when defecting a rising/falling edge of the

SCL or SDA pin. The middle-speed automatic switch wait time set

bit can select the switch timing from the low-speed to the middle-

speed mode; either 4.5 to 5.5 machine cycles or 6.5 to 7.5

machine cycles in the low-speed mode. Select it according to os-

cillation start characteristics of used XIN oscillator.

The middle-speed mode automatic switch start bit is used to auto-

matically make to XIN oscillation start and switch to the

middle-speed mode by setting this bit to “1” while operating in the

low-speed mode.

XCIN

XCOUT

“1” “0”

Port XC

switch bit

XIN

XOUT Main clock division ratio

selection bits (Note)

Low-speed mode

1/2

1/4 1/2

High-speed or

middle-speed

mode

Prescaler 12

FF16

Timer 1

Reset or

0116 STP instruction

Main clock stop bit

Main clock division ratio

selection bits (Note)

Middle-speed mode

High-speed or

low-speed mode

Timing φ (internal clock)

QS

R

STP instruction

SQ

WIT instruction

R

QS

R

STP instruction

Reset

Interrupt disable flag l

Interrupt request

Note: Any one of high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.

When low-speed mode is selected, set port Xc switch bit (b1) to “1”.

Fig. 35 System clock generating circuit block diagram (Single-chip mode)

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